Abstract: A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.

Abstract: A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.

Abstract: An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module and a second memory module, each comprising a plurality of memory devices; and a memory controller operably coupled to the first memory module and the second memory module, the memory controller operable to use an error correction code (ECC) word, comprising data and redundant data, to detect module-level errors in the first and second memory modules.

Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

Abstract: In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.

Abstract: In a preferred embodiment, the invention provides a method for determining soft and hard errors in memory. First one or more errors are detected in memory. Next correct data is written back to the memory locations were the error(s) were detected. Data is then read from the memory locations where the correct data was written. If the data that was read is correct, the memory locations where error(s) were detected are written to a register block indicating a soft error. If the data that was read is not correct, the memory locations where error(s) were detected are written to a register block indicating a hard error.

Abstract: A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a plurality of memory devices. A first error correction engine is provided for correcting device-level errors associated with a specific memory device and a second error correction engine for correcting errors at a memory module level, wherein the first and second error correction engines are operable in association with a memory controller operably coupled to the plurality of memory modules.

Abstract: A power throttling method and system for a memory controller. In one embodiment, at least a first and a second throttle value are provided in the memory controller, the first and second throttle values for controlling memory operation cycles issued by the memory controller to one or more memory devices. Responsive to a throttle control signal, the memory controller selects a lower value of the first and second throttle values, whereby the memory operation cycles are issued to the memory devices at a reduced rate.

Abstract: In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed data signals, the delayed data signals, the clock signal, and the data signal from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed data signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit. The delay of the second delayed data signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.

Abstract: In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit. The delay of the second delayed clock signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.

Abstract: The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.

Abstract: Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.

Abstract: Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.

Abstract: In a first example content addressable memory (CAM) system, an input bit pattern is compared to a plurality of identical stored bit patterns. The CAM system generates a hit signal when a match is found for at least one of the identical stored bit patterns. As a result, the system generates a false miss signal only if false matches result for all the identical stored bit patterns. In alternative examples, the system output generates a hit signal when at least half of the identical stored bit patterns match the input bit patterns, or alternatively when a majority of the identical stored bit patterns match the input bit patterns.

Abstract: The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.