Abstract: An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus.

Abstract: The embodiments provide schemes for micro parallelization.

Abstract: An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus.

Abstract: The present invention is a method and system of reusing a local memory space in a computer. In accordance with the invention an incoming stream of computer instructions is analyzed by an executable module to determine the presence of a first predetermined operator in the stream of computer instructions. If the first predetermined operator is present, the present invention determines the value of a parameter following the first operator in the stream and the executable module interposes a second operator in place of the first operator and reuses a local memory space to store an instance of the parameter in the memory space in response to the execution of the second operator.

Abstract: A data storage medium having the ability to recover from media errors includes a directory located at any desired region of a data storage area with redundant directory pointers at reserved locations. A unique file token is included in the directory entry for each data file and is also included in each extent list where the locations of parts of a fragmented data file are stored. Multiple extent lists are chained in two directions to facilitate reconstruction of the chain if part of the pointer information is lost.

Abstract: A removable optical disk of the write once type is managed to minimize size of the control area for user data recorded on the disk. Instead of recording each recorded file indicating token (serial number) as each file is recorded, a maximum value file token having a numerical value greater than a previous maximum value token is recorded in the control area such that any optical recorder receiving the disk may start recording data using such maximum value token. If the file indicating token values reach the maximum value token, then a new maximum value token is created. A pseudo end of volume (EOV) value is maintained which points to a one of the addressable data storing ares of the disk which is allocated and not recorded as EOV. All allocated data storing areas with addresses greater than EOV are recorded in contiguously addressed data storing areas. When any data storing area having an address higher than EOV is left unrecorded, then EOV is updated to point to that unrecorded allocated data storing area.

Abstract: Task dispatching for an asymmetric or symmetric multiprocessor system is provided where all the processors are dispatched from a single task dispatching queue. The workload, i.e. tasks, of the multiprocessor system is distributed to the available processors. Each processor includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system.

Abstract: An apparatus provides synchronization for page replacement control in a paged, virtual memory environment in which either the CPU or the I/O devices may pin and unpin pages to control their replacement by the paging supervisor. Pinning and unpinning of pages by the I/O devices occurs independently of pinning and unpinning performed by the CPU. Synchronization is achieved by means of a virtual address translation mechanism which is common to the CPU and the I/O devices. The virtual address translation mechanism includes a primary directory having entries for each page in main storage, with each entry containing a field in which the pinning and unpinning operations by the CPU and the I/O devices are registered. In particular, this field is a counter which is incremented when a page is pinned by either the CPU or an I/O device and decremented when a page is unpinned.