Abstract: A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.

Abstract: A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.

Abstract: A process is provided for treating coolant fluid used in wire-saw cutting of semiconductor wafers and which contains silicon-containing impurities. The process comprises changing the properties of the used coolant fluid so that the silicon-containing impurities may be filtered and separated from the coolant fluid to thereby yield a coolant fluid filtrate suitable for use in a wire-saw cutting operation.

Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Abstract: Processes for the purification of silicon carbide structures, including silicon carbide coated silicon carbide structures, are disclosed. The processes described can reduce the amount of iron contamination in a silicon carbide structure by 100 to 1000 times. After purification, the silicon carbide structures are suitable for use in high temperature silicon wafer processing.

Abstract: A wafer support for supporting a semiconductor wafer during a process including varied temperature. The wafer support includes a body having a top surface adapted to receive the semiconductor wafer so a portion of the top surface supports the wafer. The top surface has a recessed area including an inclined surface rising from a bottom of the recessed area. The inclined surface has an incline angle that is no more than about ten degrees.

Abstract: Processes for the purification of silicon carbide structures, including silicon carbide coated silicon carbide structures, are disclosed. The processes described can reduce the amount of iron contamination in a silicon carbide structure by 100 to 1000 times. After purification, the silicon carbide structures are suitable for use in high temperature silicon wafer processing.

Abstract: Processes for cleaning a silicon body and for controllably decreasing the thickness of a silicon dioxide layer overlying a silicon substrate are disclosed. The processes comprise chemically etching a silicon dioxide layer with a dilute etchant in the presence of a megasonic field. The concentration of the etchant is preferably less than its diffusion-rate-limiting threshold concentration at a given temperature. When aqueous alkaline hydroxyl ion etchants are employed, the concentration of etchant is preferably less than about 300 ppm by weight relative to water. The etching is discontinued before the silicon substrate is exposed to the etchant. The etch rate is controlled to within about 2.times.10.sup.-5 .mu.m/min (0.2 .ANG./min) of a target etch rate which ranges from about 3.times.10.sup.-5 .mu.m/min (0.3 .ANG./min) to about 4.times.10.sup.-4 .mu.m/min (4.0 .ANG./min). A simpler, more cost-effective chemical process for robustly cleaning silicon bodies or for producing very thin gate oxides is achieved.