Abstract: One or more Wireless Access Points (WAPs) are provided for a transportation vehicle. One WAP includes a combined board having a first area with micro-processor components and a second area with antenna elements, the second area located at a periphery of the combined board; a metallic cover placed over the first area; and a non-metallic cover placed over the metallic cover and the second area.

Abstract: A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.

Abstract: A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.

Abstract: A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.

Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

Abstract: A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

Abstract: High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

Abstract: High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

Abstract: In one embodiment, a personal television broadcasting system includes one or more television receivers; and a television signal transmitter coupled to one of: a personal computer, a set top box, a game console, and a portable video player to broadcast video content to the one or more television receivers that are limited within a range of a personal area. In one embodiment, a television signal transmitter is integrated with one of: a personal computer, a set top box, a game console, and a portable video player.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

Abstract: High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.