Abstract: A method for generating test patterns to detect an electric shortcircuit, a method for testing electric circuitry while using test patterns so generated, and a tester device for testing electric circuitry with such test patterns. If electric circuitry comprises a plurality of separate nets, a short circuit between an arbitrary pair of nets may be detected by driving the first net at logic zero and the second net at logic one. Measuring the two effective net potentials of the pair of nets will then reveal the short in that two equal potentials would occur. In the case of CMOS technology the driving patterns should also comprise the inverse of the combination above, and also for each pair of nets the number of non-identical overall patterns having the particular 1/0 and 0/1 combinations should be guaranteed and adjustable. The total number of patterns should be minimal. In a test pattern matrix, each column is a single overall pattern; each row is the sequence of signals for the net in question.

Abstract: Additional logic is added to a sequential finite-state machine circuit having a self-initialing behavior so that the circuit can be simulated. From any state, a rest state is reached by way of a given sequence of values of an input signal. Transitions between states of the finite-state machine are realized by the additional logic, such that the simulated circuit realizes the transition from an unknown state to a known, absorbing state in steps.

Abstract: An electronic, digital IC module includes a substrate element on which is formed a test integrated circuit for the execution of a boundary scan on a standard integrated circuit formed on another substrate element. Either the substrate for the test circuit is provided in an electronic sub-module on which is formed a test socket, in which case the standard circuit is mounted piggy-back, or a hybrid package is provided composed of the two substrate elements which are interconnected by bond pads. The test circuit includes a shift register for parallel connection to the standard circuit and serial connection to an external test unit.