Abstract: In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Abstract: Techniques, systems, and devices are disclosed that relate to coaxial photoconductive switch modules. The coaxial photoconductive switch may include an outer conductor, an inner conductor, and a photoconductive material positioned between the inner conductor and the outer conductor. The inner conductor, the outer conductor, and the photoconductive material have a predetermined height. A bias voltage may be applied between the inner conductor and the outer conductor. When light of a predetermined wavelength and a predetermined intensity is incident on the photoconductive material, the photoconductive material may break down allowing a current to flow through the photoconductive material between the inner conductor and the outer conductor.

Abstract: Techniques, systems, and devices are disclosed that relate to coaxial photoconductive switch modules. The coaxial photoconductive switch may include an outer conductor, an inner conductor, and a photoconductive material positioned between the inner conductor and the outer conductor. The inner conductor, the outer conductor, and the photoconductive material have a predetermined height. A bias voltage may be applied between the inner conductor and the outer conductor. When light of a predetermined wavelength and a predetermined intensity is incident on the photoconductive material, the photoconductive material may break down allowing a current to flow through the photoconductive material between the inner conductor and the outer conductor.

Abstract: Techniques, systems, and devices are disclosed that relate to coaxial photoconductive switch modules. The coaxial photoconductive switch may include an outer conductor, an inner conductor, and a photoconductive material positioned between the inner conductor and the outer conductor. The inner conductor, the outer conductor, and the photoconductive material have a predetermined height. A bias voltage may be applied between the inner conductor and the outer conductor. When light of a predetermined wavelength and a predetermined intensity is incident on the photoconductive material, the photoconductive material may break down allowing a current to flow through the photoconductive material between the inner conductor and the outer conductor.

Abstract: A photoconductive switch consisting of an optically actuated photoconductive material, e.g. a wide bandgap semiconductor such as SiC, situated between opposing electrodes. The electrodes are created using various methods in order to maximize reliability by reducing resistive heating, current concentrations and filamentation, and heating and ablation due to the light source. This is primarily accomplished by the configuration of the electrical contact geometry, choice of contacts metals, annealing, ion implantation, creation of recesses within the SiC, and the use of coatings to act as encapsulants and anti-reflective layers.

Abstract: According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Abstract: In various approaches room-temperature gamma detector longevity may be improved by selectively removing, or selectively incorporating, alternate halogen component(s) from select surfaces of the detector. According to one embodiment, a method of improving operational longevity of a thallium bromide (TlBr)-based detector includes: selectively treating one or more surfaces of the TlBr-based detector to produce a surface substantially comprising pure TlBr. Similar techniques may be employed to restore a degraded or failed detector. According to another embodiment, a method of forming a TlBr-based detector exhibiting improved operational longevity includes: selectively treating one or more surfaces of the TlBr-based detector to replace Br therein with one or more alternate halogen components while also substantially avoiding replacing some or all of the Br in other surfaces of the TlBr-based detector with the one or more alternate halogen components.

Abstract: According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Abstract: In various approaches room-temperature gamma detector longevity may be improved by selectively removing, or selectively incorporating, alternate halogen component(s) from select surfaces of the detector. According to one embodiment, a method of improving operational longevity of a thallium bromide (TlBr)-based detector includes: selectively treating one or more surfaces of the TlBr-based detector to produce a surface substantially comprising pure TlBr. Similar techniques may be employed to restore a degraded or failed detector. According to another embodiment, a method of forming a TlBr-based detector exhibiting improved operational longevity includes: selectively treating one or more surfaces of the TlBr-based detector to replace Br therein with one or more alternate halogen components while also substantially avoiding replacing some or all of the Br in other surfaces of the TlBr-based detector with the one or more alternate halogen components.

Abstract: A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of ˜0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.

Abstract: A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of ˜0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.

Abstract: A photoconductive switch consisting of an optically actuated photoconductive material, e.g. a wide bandgap semiconductor such as SiC, situated between opposing electrodes. The electrodes are created using various methods in order to maximize reliability by reducing resistive heating, current concentrations and filamentation, and heating and ablation due to the light source. This is primarily accomplished by the configuration of the electrical contact geometry, choice of contacts metals, annealing, ion implantation, creation of recesses within the SiC, and the use of coatings to act as encapsulants and anti-reflective layers.

Abstract: In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

Abstract: According to one embodiment, a product includes an array of three dimensional structures, a cavity region between each of the three dimensional structures, and a first material in contact with at least one surface of each of the three dimensional structures. In addition, each of the three dimensional structures includes a semiconductor material, where at least one dimension of each of the three dimensional structures is in a range of about 0.5 microns to about 10 microns. Moreover, the first material is configured to provide high energy particle and/or ray emissions.

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

Abstract: In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

Abstract: In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

Abstract: In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.

Abstract: According to one embodiment, an apparatus for detecting neutrons includes an array of pillars, wherein each of the pillars comprises a rounded cross sectional shape where the cross section is taken perpendicular to a longitudinal axis of the respective pillar, a cavity region between each of the pillars, and a neutron sensitive material located in each cavity region.