Patents by Inventor Laun C. Tran

Laun C. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9747159
    Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yue-Der Chih, Hung-Chang Yu, Kai-Chun Lin, Chin-Yi Huang, Laun C. Tran
  • Publication number: 20150355963
    Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Yue-Der Chih, Hung-Chang Yu, Kai-Chun Lin, Chin-Yi Huang, Laun C. Tran
  • Patent number: 9110829
    Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Yue-Der Chih, Hung-Chang Yu, Kai-Chun Lin, Chin-Yi Huang, Laun C. Tran
  • Publication number: 20140157088
    Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.
    Type: Application
    Filed: June 14, 2013
    Publication date: June 5, 2014
    Inventors: Yue-Der Chih, Hung-Chang Yu, Kai-Chun Lin, Chin-Yi Huang, Laun C. Tran