Patents by Inventor Laura J. Schutz
Laura J. Schutz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190363160Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.Type: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Inventors: Siva P. ADUSUMILLI, Anthony K. STAMPER, Laura J. SCHUTZ, Cameron E. Luce
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Patent number: 10446643Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.Type: GrantFiled: January 22, 2018Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Siva P. Adusumilli, Anthony K. Stamper, Laura J. Schutz, Cameron E. Luce
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Patent number: 10411107Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.Type: GrantFiled: September 1, 2017Date of Patent: September 10, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Laura J. Schutz, Anthony K. Stamper, Siva P. Adusumilli, Joshua F. Dillon
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Publication number: 20190229185Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.Type: ApplicationFiled: January 22, 2018Publication date: July 25, 2019Inventors: Siva P. ADUSUMILLI, Anthony K. STAMPER, Laura J. SCHUTZ, Cameron E. Luce
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Publication number: 20190074364Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.Type: ApplicationFiled: September 1, 2017Publication date: March 7, 2019Inventors: Laura J. Schutz, Anthony K. Stamper, Siva P. Adusumilli, Joshua F. Dillon
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Patent number: 9397174Abstract: A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion.Type: GrantFiled: October 17, 2014Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Publication number: 20150035076Abstract: A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Patent number: 8932920Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.Type: GrantFiled: May 29, 2013Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Publication number: 20140353759Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.Type: ApplicationFiled: May 29, 2013Publication date: December 4, 2014Applicant: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
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Patent number: 8796130Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.Type: GrantFiled: January 18, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz
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Publication number: 20130181293Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Applicant: International Business Machines CorporationInventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz