Abstract: In an approach to integrated circuit track coloring, system ground rules, minimum wire width, minimum spacing, and a set of one or more colors, are received. A track layout is created. A first color is assigned to each power track. A second color is assigned to each wide track. One or more legal colors are determined for each minimum width track. A legal color is assigned to each minimum width track.

Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.

Abstract: Embodiments of the invention are directed to methods, systems, and computer program products for the hierarchical management of self-aligned double patterning (SADP) trim shapes. Non-limiting embodiments of the invention include receiving, by a processor, one or more virtual trim shapes at a boundary between a parent hierarchy block and a child hierarchy block. The trim shapes are aligned to a legal trim grid. The processor then places one or more trim shapes aligned with the legal trim grid.

Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.

Abstract: Embodiments of the invention are directed to methods, systems, and computer program products for the hierarchical management of self-aligned double patterning (SADP) trim shapes. Non-limiting embodiments of the invention include receiving, by a processor, one or more virtual trim shapes at a boundary between a parent hierarchy block and a child hierarchy block. The trim shapes are aligned to a legal trim grid. The processor then places one or more trim shapes aligned with the legal trim grid.

Abstract: Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.

Abstract: Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.

Abstract: A method, system and program product are disclosed that create new shapes at detected shape overlaps and includes those new shapes during routing and net checking when the new shapes require a larger space than any of the overlapping shapes. The invention thus detects and prevents spacing errors without the expense of time consuming design rule checking (DRC), facilitating early detection and prevention of errors.

Abstract: A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.

Abstract: A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.

Abstract: A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.

Abstract: A structure and method for testing spacing of wiring in a circuit comprises forming a plurality of conductor rectangles representative of conductors of the circuit, forming minimum spacing rectangles around the conductor rectangles (the minimum spacing rectangles being larger than respective ones of the conductor rectangles), identifying a possible error rectangle when a first conductor rectangle of the conductor rectangles occupies a portion of a minimum spacing rectangle of a second conductor rectangle of the conductor rectangles, checking whether the possible error rectangle is a true error, and reporting the true errors.

Abstract: A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.