Patents by Inventor Laurence Boissonnet

Laurence Boissonnet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit comprising a gradually doped bipolar transistor and corresponding fabrication process
    Patent number: 8168504
    Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: May 1, 2012
    Assignee: STMicroelectronics SA
    Inventors: Damien Lenoble, Thierry Schwartzmann, Laurence Boissonnet
  • INTEGRATED CIRCUIT COMPRISING A GRADUALLY DOPED BIPOLAR TRANSISTOR AND CORRESPONDING FABRICATION PROCESS
    Publication number: 20100167488
    Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: STMICROELECTRONICS SA.
    Inventors: Damien Lenoble, Thierry Schwartzmann, Laurence Boissonnet
  • Integrated circuit comprising a gradually doped bipolar transistor
    Patent number: 7705427
    Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: April 27, 2010
    Assignee: STMicroelectronics SA
    Inventors: Damien Lenoble, Thierry Schwartzmann, Laurence Boissonnet
  • INTEGRATED CIRCUIT COMPRISING A GRADUALLY DOPED BIPOLAR TRANSISTOR AND CORRESPONDING FABRICATION PROCESS
    Publication number: 20070108555
    Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 17, 2007
    Applicant: STMicroelectronics SA
    Inventors: Damien Lenoble, Thierry Schwartzmann, Laurence Boissonnet
  • Method of simultaneously making a pair of transistors with insulated gates having respectively a thin oxide and a thick oxide, and corresponding integrated circuit comprising such a pair of transistors
    Patent number: 7015105
    Abstract: A method of simultaneously fabricating a pair of insulated gate transistors respectively having a thin oxide and a thick oxide, and an integrated circuit including a pair of transistors of this kind. Forming low-doped NLDD areas of the thin oxide second transistor includes implanting a first dopant having a first concentration and implanting a second dopant having a second concentration lower than the first concentration. Forming low-doped areas NLDD of the first, thick oxide transistor includes only said implantation of the second dopant.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: March 21, 2006
    Assignee: STMicroelectronics, S.A.
    Inventors: Laurence Boissonnet, Dominique Golanski, Bruno Rauber, Andre Granier
  • Method of simultaneously making a pair of transistors with insulated grids having respectively a fine oxide and a thick oxide, and corresponding integrated circuit comprising such a pair of transistors
    Publication number: 20030155618
    Abstract: Forming low-doped NLDD areas 17, 61 of the thin oxide second transistor T2 includes implanting a first dopant 16 having a first concentration and implanting a second dopant 22 having a second concentration lower than the first concentration. Forming low-doped areas NLDD 61 of the first, thick oxide transistor T1 includes only said implantation of the second dopant 22.
    Type: Application
    Filed: June 27, 2002
    Publication date: August 21, 2003
    Inventors: Laurence Boissonnet, Dominique Golanski, Bruno Rauber, Andre Granier