Abstract: A solar antenna array may comprise an emitter that may convert visible light into black body infrared radiation, and an array of antennas that may capture and convert the black body radiation into electrical power. Methods for constructing the solar antenna array may include using thermal insulation, high-gain low-e glass, and gasses with minimal heat transfer. A black body infrared antenna array may augment the electrical power from a visible light antenna array by converting its waste heat into additional electrical power.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: A semi-reflective display and a method for fabricating and assembling a semi-reflective display are presented, where the display may be comprised of visible light rectifying antenna arrays tuned to four different colors, which when forward biased may use electric power to amplify reflected colored light, and when reversed biased may generate electric power by absorbing light. TFT-tunnel diode logic may be used to control each sub-pixel.

Abstract: Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss. Information may be similarly encoded in magnetic moments of spins of pairs of positrons and electrons, not in the form of Cooper pairs.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-fop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: A semi-reflective display and a method for fabricating and assembling a semi-reflective display are presented, where the display may be comprised of visible light rectifying antenna arrays tuned to four different colors, which when forward biased may use electric power to amplify reflected colored light, and when reversed biased may generate electric power by absorbing light. TFT-tunnel diode logic may be used to control each sub-pixel.

Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

Abstract: Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: A solar antenna array may comprise an array of randomly placed carbon nanotube antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may use a mold and self aligning processing steps to minimize cost. Designs may be optimized for capturing a broad spectrum of non-polarized light. Alternatively, the array may generate light, and when connected in to an array of independently controllable sections may operate as either a reflective or light transmitting display.

Abstract: Hydro-carbon nanorings may be used, e.g., in power storage power transmission and transportation. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole containment field for electrons rotating in the nanoring. Such nanorings may transmit DC current with little or no loss. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole containment field for positrons rotating in the nanoring. Virtually lossless transmission of AC current may be achieved by pairing such streams of electrons and positrons in their respective containment fields. Closed rotation of such streams may also be used to efficiently store large amounts of electrical energy. Finally, selectively accelerating and decelerating pairs of such paired electron and positron streams, which are moving at relativistic speeds, differential momentum may be created to cause physical movement.

Abstract: A solar antenna array may comprise an array of antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may use a stencil and self aligning semiconductor processing steps to minimize cost. Designs may be optimized for capturing a broad spectrum of visible light and non-polarized light. Testing and disconnecting defective antennas from the array may also be performed.

Abstract: A semi-reflective display and a method for fabricating and assembling a semi-reflective display are presented, where the display may be comprised of visible light rectifying antenna arrays tuned to four different colors, which when forward biased may use electric power to amplify reflected colored light, and when reversed biased may generate electric power by absorbing light. TFT-tunnel diode logic may be used to control each sub-pixel.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

Abstract: Hydro-carbon nanorings may be used, e.g., in power storage power transmission and transportation. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole containment field for electrons rotating in the nanoring. Such nanorings may transmit DC current with little or no loss. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole containment field for positrons rotating in the nanoring. Virtually lossless transmission of AC current may be achieved by pairing such streams of electrons and positrons in their respective containment fields. Closed rotation of such streams may also be used to efficiently store large amounts of electrical energy. Finally, by selectively accelerating and decelerating pairs of such paired electron and positron streams, which are moving at relativistic speeds, differential momentum may be created to cause physical movement.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.