Abstract: A transceiver comprising: a transmitter configured to transmit a signal comprising differential voltages to at least a first terminal and a second terminal; at least one receiver; a controller configured to provide control signals to the transmitter to cause the transmitter to transmit symbols, wherein each symbol comprises a predefined set of said differential voltages including at least a positive differential voltage and a negative differential voltage; and a signal balance module configured, for one or more symbols, to: determine a first duration of the positive differential voltage of said one or more symbols; determine a second duration of the negative differential voltage of said one or more symbols; based on determination of a difference between the first and second durations, provide for control of the controller or control of the transmitter to reduce the difference between the first and second durations in a further symbol relative to the one or more symbols.

Abstract: The present invention relates to a DC-DC boost converter which ensures a fast start until the desired output voltage is reached without causing a high input current during the start phase. In particular, the limitation of the input current is influenced according to the initial output voltage. The invention also relates to a method for the boost converter.

Abstract: The disclosure relates to a switchable termination resistance circuit for a transceiver physical layer interface. Example embodiments include a switchable termination resistance circuit (301) for a transmission line transceiver (801), the switchable termination resistance circuit (301) comprising: first and second terminals (TXP, TXN) for connection to a transmission line (103); first and second NMOS termination resistance switches (Mnsw1, Mnsw2) having source connections connected together at a midpoint node (303) and gate connections connected to an input node (304); a first resistor (R1) connected between the first terminal (TXP) and a drain connection of the first NMOS termination resistance switch (Mnsw1); a second resistor (R2) connected between the second terminal (TXN) and a drain connection of the second NMOS termination resistance switch (Mnsw2); and a Zener diode (Dz1) having a cathode side connected to the input node (304) and an anode side connected to the midpoint node (303).

Abstract: The present disclosure relates to a transceiver (100) comprising a first and second terminal, a signal generation unit a signal generation unit (110) for generating a differential output voltage (Vout) between the terminals, a sensor unit (112) configured to measure an electric current (Iout) when flowing through one of the terminals, and a control unit (114) for controlling the signal generation unit, wherein the control unit is configured to control the signal generation unit during a calibration phase to generate a predetermined differential output voltage reference pattern (140), wherein the sensor unit is configured to measure a calibration current unit during the calibration phase, and wherein the control unit is configured to calibrate the signal generation unit depending on the calibration current. The present disclosure also relates to a method for the transceiver.

Abstract: A pulse stretcher is disclosed comprising, a stretcher input (10) and a stretcher output (20); an asynchronous finite state machine; and a delay generator (40) having a delay input connected to the stretcher output, and a delay output connected to a second input of the FSM. The asynchronous FSM comprises: a first Muller C-element gate (250) having an output connected to the stretcher output, a second Muller C-element gate (260) having an output; and a combinatorial logic circuit (270) connected to the stretcher input, to first and second inputs of each of the first and second C-elements. The first and second Muller C-element gates are cross-coupled via the combinatorial logic, such that the respective outputs of the C-element gates are complementary and, in response to receiving the input pulse at the stretcher input, the output of the first Muller C-element gate provides a stretched version of the input pulse.

Abstract: A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels.

Abstract: A pulse stretcher is disclosed comprising, a stretcher input (10) and a stretcher output (20); an asynchronous finite state machine; and a delay generator (40) having a delay input connected to the stretcher output, and a delay output connected to a second input of the FSM. The asynchronous FSM comprises: a first Muller C-element gate (250) having an output connected to the stretcher output, a second Muller C-element gate (260) having an output; and a combinatorial logic circuit (270) connected to the stretcher input, to first and second inputs of each of the first and second C-elements. The first and second Muller C-element gates are cross-coupled via the combinatorial logic, such that the respective outputs of the C-element gates are complementary and, in response to receiving the input pulse at the stretcher input, the output of the first Muller C-element gate provides a stretched version of the input pulse.

Abstract: A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller.

Abstract: A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels.

Abstract: A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller.

Abstract: A controller system controls a plurality of lighting element arrays. The controller system comprises array selection module for selecting a lighting element array, voltage control module arranged to apply a voltage to at least the selected lighting element array, a common current source arranged to provide a current from the common current source to the selected lighting element array, and duty cycle control module arranged to control a ratio of the current to the selected lighting element array over a time sharing cycle.

Abstract: A controller system controls a plurality of lighting element arrays. The controller system comprises array selection module for selecting a lighting element array, voltage control module arranged to apply a voltage to at least the selected lighting element array, a common current source arranged to provide a current from the common current source to the selected lighting element array, and duty cycle control module arranged to control a ratio of the current to the selected lighting element array over a time sharing cycle.