Abstract: A receiver is disclosed, wherein a re-ordering means comprises a multiplexer, a finite-state machine, and a plurality of buffers. the finite-state machine is arranged to control the multiplexer to load the buffers from a bus such that the output of the buffers is directly decodable by the decoder. A receiving method is also disclosed, comprising the steps of: determining a transmission mode and a bus configuration; entering an initializing state of branching of a finite-state machine according to said determined transmission mode and bus configuration; performing transitions between state of the said finite-state machine for each received set of soft data provided on a bus; multiplexing said soft data to a plurality of buffers in dependence on the state of said finite-state machine; and writing said multiplexed data into said plurality of buffers.

Abstract: An electronic slave device includes a hardware data packing block having a configurable multiplexing unit having inputs connected to system bus, wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; a format register, the value of which can be set by an external master device to at least two different values; and a logic circuit capable of setting the connections of the multiplexing unit according to the value of the format register to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.

Abstract: The electronic slave device (6) comprises a hardware data packing block having: • a configurable multiplexing unit (44) having inputs connected to system bus (8) wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory (18) for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; • a format register (40), the value of which can be set by an external master device (4) to at least two different values; and • a logic circuit (48) capable of setting the connections of the multiplexing unit (44) according to the value of the format register (40) to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.

Abstract: A data processing arrangement (BBP) comprises a system-host processor (SHP) and a system-guest processor (SGPl). The system-host processor (SHP) is provided with an operating system (OS) and an operating-system-message transceiver (SI) for receiving an operating-system-related message corresponding with a service request and for sending an operating-system-related message corresponding with a service response. The system-guest processor (SGPl) is provided with an operating-system simulator (SOI). The operating-system simulator (SOI) sends an operating-system-related message to the system-host processor (SHP) in response to a service request from a task (A, B) that the system-guest processor carries (SGP) out. The operating-system simulator (SOI) provides a service response to the task (A, H) in response to an operating-system-related message from the system-host processor (SHP).

Abstract: A receiver is disclosed, wherein a re-ordering means comprises a multiplexer, a finite-state machine, and a plurality of buffers. The finite-state machine is arranged to control the multiplexer to load the buffers from a bus such that the output of the buffers is directly decodable by a decoder A receiving method is also disclosed, comprising the steps of: determining a transmission mode and a bus configuration; entering an initializing state of branching of a finite-state machine according to said determined transmission mode and bus configuration; performing transitions between states of said finite-state machine for each received set of soft data provided on a bus; multiplexing said soft data to a plurality of buffers in dependence on on the state of said finite-state machine; and writing said multiplexed data into said plurality of buffers.