Abstract: In general, techniques are described that enable a source device to perform level estimation for processing audio data. The source device may include a memory and a processor. The memory may store at least a portion of the audio data. The processor may obtain a current indication representative of a current level of a current block of the audio data, and obtain a previous indication representative of a previous level of a previous block of the audio data. The processor may perform, based on the current indication and the previous indication, level estimation to obtain a level estimate indication representative of an estimate of the level of the current block of the audio data. The processor may also perform, based on the level estimate indication, compression with respect to the current block of the audio data to obtain a bitstream.

Abstract: A source device comprising a memory and a processor may be configured to perform techniques described in this disclosure. The memory may store at least a portion of the audio data. The processor may obtain, from a compressed version of the audio data, a symbol, and obtain a plurality of intervals, each having a same bit length. The processor may obtain a portion of the symbol within the bit length and an excess portion of the symbol over the bit length, and specify, in a first interval, the portion of the symbol. The processor may also specify, in a second interval, the excess portion of the symbol, and apply, to the first interval and the second interval, error resiliency. The processor may specify, in a bitstream representative of the compressed version of the audio data, the first error resilient interval and the second error resilient interval.

Abstract: A first device may establish, with a second device, a short-range wireless communications link. The first device may determine a time interval between each of a set of packets to be transmitted over a short-range wireless communications link with a second device. The first device may encode data with a bitrate that is based on the time interval. The first device may packetize the encoded data in the set of packets. The first device may transmit the set of packets to the second device or the short-range wireless communications link, and each of the set of packets may be separated by the time interval when transmitted.

Abstract: In general, various aspects of techniques are described to enable application directed latency control for wireless audio streaming. A source device comprising a memory and a processor may perform the techniques. The memory may store at least a portion of audio data. The processor may execute an application that outputs the audio data, and a request for a quality of service concerning audio processing applied to the audio data. The processor may determine whether the source device is currently displaying the application, and configure, responsive to the determination that the source device is currently displaying the application, a wireless audio processing path to achieve the requested quality of service. The processor may next process, by the wireless audio processing path, the audio data to obtain a bitstream representative of the audio data.

Abstract: A system for distributing audio or video data across a network, wherein an input data rate controller at a server controls the transmission rate to a client such that it matches the intended rendering rate of the data, and time stamps the data using a clock that is synchronized with the clock of the client. The client monitors the rate at which data is received, compares the rate against the rate at which the data is actually rendered, and adjusts the rate at which the data is actually rendered depending on the comparison.

Abstract: The present application relates to methods for adapting a data rate used to generate data packets for transmission by a wireless transmitter (12) operating in a wireless network. In one method, the transmitter (12) monitors the number of data packets that cannot be transmitted in a given time period, and adjusts the data rate used for generation of data packets for transmission in accordance with the number of packets that remain un-transmitted at the end of the given time period. In another method, the transmitter (12) uses information associated with or derived from Acknowledgements received from a receiving device to determine whether an adjustment to the data rate used for generation of data packets for transmission is required. In a further method, the transmitter (12) monitors a packet error rate for transmitted packets and determines a maximum packet error rate that can be supported by the wireless network without instability.

Abstract: A system for distributing audio or video data across a network, wherein an input data rate controller at a server controls the transmission rate to a client such that it matches the intended rendering rate of the data, and time stamps the data using a clock that is synchronized with the clock of the client. The client monitors the rate at which data is received, compares the rate against the rate at which the data is actually rendered, and adjusts the rate at which the data is actually rendered depending on the comparison.

Abstract: A system for distributing audio or video data across a network, wherein an input data rate controller at a server controls the transmission rate to a client such that it matches the intended rendering rate of the data, and time stamps the data using a clock that is synchronized with the clock of the client. The client uses the time stamps and its synchronized clock signal to control the rendering of the data.

Abstract: A system for distributing audio or video data across a network, wherein an input data rate controller at a server controls the transmission rate to a client such that it matches the intended rendering rate of the data, and time stamps the data using a clock that is synchronized with the clock of the client. The client uses the time stamps and its synchronized clock signal to control the rendering of the data.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killed” later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.

Abstract: A method of executing loops in a computer system is described. The computer system has a sequence of instructions held in program memory and a prefetch buffer which holds instructions fetched from the memory ready for supply to a decoder of the computer system. If the size of the loop to be executed is such that it can by holly contained within the prefetch buffer, this is detected and a lock is put on the prefetch buffer to retain the loop within it while the loop is executed a requisite number of times. This thus allows power to be saved and reduces the overhead on the memory access buffers. According to another aspect, loops can be “skipped” by holding a value of zero in the loop counter register.

Abstract: A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.

Abstract: A computer system includes instruction fetch circuitry, decode circuitry to decode instructions and identify any registers to be used and dispatch circuitry to dispatch instructions to one or more execution units, said system including emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions, the computer circuitry further comprising a register watch store for identifying one or more registers to be watched, comparator circuitry for comparing registers identified by said decode circuitry with registers identified in said register watch store and providing a hit signal for hits in the comparison, and instruction insertion circuitry responsive to hit signals to insert in the instruction sequence to an execution unit a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data regist

Abstract: An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilized in that machine cycle.

Abstract: A storage array is described which is specifically adapted to support a specific set of instruction modes of a processor. A first set of storage cells have a write input and a single read output. Second and third sets of storage cells each have a write input and only two read outputs. A fourth set of storage cells each have a write input and only three outputs. All the write inputs are addressable in common by a single write address and the read outputs are individually selectable responsive to a read pointer.

Abstract: A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be support and hides memory access latency.

Abstract: A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.