Abstract: A computer display controller (50) cooperates with a host microprocessor (18) to direct display data to a frame buffer memory (16) in accordance with a selected one of multiple frame buffer memory configurations (20 and 30). The display controller includes an address decoder circuit (58) that delivers address information generated by the host microprocessor to the address inputs (64) of the frame buffer memory in accordance with the selected frame buffer memory configuration.

Abstract: A TFEL panel includes orthogonally disposed sets of scanning and data electrodes. The scanning electrodes are strobed with a preconditioning voltage and data is provided to selected data electrodes simultaneously with the line by line strobing of the scanning electrodes. A refresh pulse is applied to the screen once per frame of data at times which vary from frame to frame. This may be accomplished either by varying the time of occurrence of the refresh pulse within each frame or by holding the time of occurrence of the refresh pulse constant and varying the strobing sequence of the scanning electrodes. This technique prevents certain portions of the screen from generating a latent image due to charge accumulation which would otherwise result from the timing asymmetry between the scanning of certain electrodes and the fixed timing of the refresh pulse.