Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

Abstract: Architectures and techniques are presented that provide a dynamic, action-driven visual task flow customization to a software-as-a-service (SaaS) platform. A task element, expressing a task workflow can be modeled as a record of an order data model of the development environment. The task workflow can be executing according to a flow state management procedure, e.g., to manage lifecycle. In response to the flow state management procedure, the record can be updated according to a current state of the task element. These task elements can be correlated to an action or other operation of a flow designer module of the SaaS platform, which can leverage native automation.

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

Abstract: In one embodiment, an apparatus comprises a processor and a memory controller. The processor is to identify a memory access operation associated with a memory location of a memory. The processor is further to determine that a cache memory does not contain data associated with the memory location. The processor is further to send a memory access notification to a memory controller via a first transmission path. The processor is further to send a memory access request to the memory controller via a second transmission path, wherein the second transmission path is slower than the first transmission path. The memory controller is to receive the memory access notification via the first transmission path, and send a memory activation request based on the memory access notification, wherein the memory activation request comprises a request to activate a memory bank associated with the memory location.

Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.

Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.

Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.

Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

Abstract: The present disclosure discloses an embodiment for managing sustainability goals of an organization. Organizational activities associated with the sustainability goals and performed in the organization are identified. The attributes of the stakeholders of the organization are identified. A first set of activities from the plurality of organizational activities and a second set of activities associated with each of the stakeholders of the organization are determined. Based on the one or more attributes, the first set of activities and the second set of activities, a first sustainability goal to the stakeholders of the organization is assigned. Further, a first set of data corresponding to the first set of activities, a second set of data corresponding to the second set of activities associated with each of the stakeholders are extracted. Based on the first set of data and the second set of data for each of the stakeholders, a personal sustainability index is determined.