Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

Abstract: Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.

Abstract: A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Abstract: An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.

Abstract: A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Abstract: An interconnect structure for an integrated circuit includes a plurality of first-type interconnect elements and a second-type of interconnect element which directly contact an underlying first-type interconnect element. The second-type interconnect element extends along a first axis to define a horizontal length and along a second axis to define a vertical height. The second-type interconnect element and the first-type interconnect element define a conductive via comprising a metal material extending continuously along the second axis from a base of the underlying first-type interconnect element and stopping at the upper surface of the second-type interconnect element. The vertical height of the second-type interconnect element is greater than the vertical height of the first-type interconnect elements.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring, a second level of interconnect wiring disposed above the first level of interconnect wiring, a third level of interconnect wiring disposed above the second level of interconnect wiring, and a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. A contact area between the sidewall of the skip via and the second level of interconnect wiring is greater than a contact area between a bottom portion of the skip via and a top portion of the first level of interconnect wiring.

Abstract: A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Abstract: A semiconductor structure comprises a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.

Abstract: A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.

Abstract: Semiconductor device and methods of forming the same include a semiconductor channel. A top source/drain structure is on the semiconductor channel. A bottom source/drain structure is under the semiconductor channel. The bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer that includes a first transistor device. A first back-end-of-line (BEOL) layer is on a front side of the FEOL layer and includes a first electrical connection to the first transistor device. A second BEOL layer is on a back side of the FEOL layer and includes a first BEOL device with a second electrical connection to the first transistor device.

Abstract: An interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: A semiconductor device includes an isolation region and at least one transistor including a gate region, wherein the gate region is disposed on the isolation region. A via is disposed through a portion of the isolation region and on a signal line. A gate contact is disposed on the gate region. The via is connected to the gate contact and the signal line is connected to the gate region through the via and the gate contact.

Abstract: A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.