Abstract: Apparatus and methods for expanding a data transfer framework are disclosed. Exemplary implementations may: provide an ETL framework comprising a plurality of ETL modules and comprising code including variables; obtain a configuration file including data values to replace the variables for executing selected ETL modules, and including external command data configured to execute a new data transformation external to and absent from the ETL framework, the external command data including a reference to an external module generated in relation to an external interface; and execute the one or more selected ETL modules based on the code, the data values and the external command data. Exemplary implementations provide a flexible and expandable ETL framework that enable a new type of data transformation that is not currently supported by the framework, without having to modify the framework. The framework may impart native properties and characteristics of the framework to the external module.

Abstract: The invention relates to compounds of the formula (I) R1—Q1—X—Q2—R2, in which: Q1, Q2, each independent of one another, are missing or are —NH—(CH2)n—CO—; R1, R2, each independent of one another, are missing or are cyclo-(Arg-Gly-Asp-Z), wherein Z is missing in side chain of Q1 or Q2 of if Q1 and/or Q2 missing, is bound to X, at least one of the groups R1 or R2 always having to be included; X is —CO—R18—CO—, and if R1—Q1— or R2—Q2— are missing is R10, R13, Het-CO or a flourescent pigment residue linked through a —CONH—, —COO—, NH—C(═S)—N—, —NH—C(═O)—NH—, —SO2 NH—or —NHCO— bond; and Z, R10, R13, R16, R18, Het and n have the meaning given in claim 1. The invention also relates to the salts of said compounds.

Abstract: A method of adjusting the position of a micro-mechanical bi-material cantilever is provided. The bi-material includes a first and a second material and each material has a corresponding thermal expansion coefficient. The method includes implanting ions predominantly into one material of the bi-material to modify internal stress in one of the first and second materials relative to the other material. The deformation of the bi-material is then detected to modulate the implantation of ions thereto.

Abstract: The invention relates to compounds of the formula (I) R1 Q1 XQ2 R2, in which: Q1, Q2, each independent of one another, are missing or are NH(CH2)n CO; R1, R2, each independent of one another, are missing or are cyclo(ArgGlyAspZ), wherein Z is missing in the side chain of Q1 or Q2 or if Q1 and/or Q2 are missing, is bound to X, at least one of the groups R1 or R2 always having to be included; X is COR 18 CO, and if R1 Q1 or R2 Q2 are missing is R10, R13, R16, HetCO or a fluorescent pigment residue linked through a CONH, COO, NHC (═S)NH, NHC(═O)NH, SO2 NH or NHCO bond; and Z, R10, R13, R16, R18, Het and n have the meanings given in claim 1. The invention also relates to the salts of said compounds. Said compounds and their salts can be used as integrin inhibitors, in particular for the prevention and treatment of circulatory diseases, thrombosis, heart infarct, coronary heart diseases, arteriosclerosis, angiogenic diseases and in tumor therapy.

Abstract: A method of etching an opening having tapered wall in a layer of silicon carbide (SiC) includes forming a layer of a resist on the SiC layer. An opening having tapered wall is formed in the resist layer so as to expose a portion of the SiC layer. The exposed portion of the SiC layer is then exposed to a plasma of a gas containing carbon and fluorine to etch an opening through the SiC layer with the opening having tapered walls. If a layer of a glass is provided under the SiC layer, the plasma will also etch through the glass layer to provide an opening in the glass layer having tapered walls.

Abstract: A circuit in accordance with the invention has a complementary pair of a MISFET and a COMFET with their drains connected together. This allows fabrication on a single substrate for greater reliability and reduced cost. The circuit can be used in a full or one half "H-bridge" configuration for controlling current through a load such as a motor.

Abstract: A circuit in accordance with the invention has a complementary pair of a MISFET and a COMFET with their drains connected together. This allows fabrication on a single substrate for greater reliability and reduced cost. The circuit can be used in a full or one half "H-bridge" configuration for controlling current through a load such as a motor.

Abstract: A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.

Abstract: A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped.

Abstract: A method for decreasing the turnoff time in a crystalline semiconductor region within a semiconductor device comprises initially providing a semiconductor region having a predetermined density of pinning centers. The semiconductor region is then irradiated so as to yield crystal damage that is equivalent to or greater than that which would be produced by irradiating with 1 MeV neutrons at a fluence greater than approximately 10.sup.13 cm.sup.-2. The region is then annealed at a temperature of approximately 350.degree. to 450.degree. C. for approximately 15 minutes to one hour so as to yield a density of stable recombination centers correlating with the pinning centers that provides a stable minority carrier lifetime within the semiconductor region.

Abstract: A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped.

Abstract: A method for revealing the presence of heavy metal impurities that may have been introduced during the formation of a layer, such as the deposition of an epitaxial layer on a semiconductor substrate, uses the constant-magnitude steady-state surface photovoltage (SPV) method for determining the minority-carrier diffusion length by essentially two determination steps. A large ratio of the respective diffusion lengths determined before (actually measured or based on a priori knowledge of similar material) and after the epitaxial deposition step is indicative of the presence of a heavy metal impurity in the epitaxial layer. The method is based on the fact that the contaminating metal distributes itself substantially uniformly not only through the epitaxial layer but also throughout the substrate.

Abstract: A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.

Abstract: A MOSFET device having minimized parasitic bipolar effects comprises a substrate having a surface at which source and drain regions are spaced so as to define a channel portion in a body region. The channel portion is formed in a relatively low conductivity portion of the body region, the remainder of the body region being of higher conductivity. A gate overlies the channel portion, and a method for automatically aligning the gate to a grooved MOSFET is described.

Abstract: A vertical MOSFET structure which includes a drain which comprises a high conductivity region and a low conductivity region. The high conductivity drain region is contoured so as to minimize the device turn-on resistance without degrading the device breakdown voltage.

Abstract: An apertured mask is formed on a major surface of a semiconductor substrate, and a groove is generated in the semiconductor in an area exposed by the aperture. A layer of electrode material is then formed on the groove surface, the layer extending beyond the groove and onto the mask. The mask is then stripped, and those portions of the electrode material extending beyond the groove are removed.

Abstract: A transistor comprises two spaced apart electrodes, a body of semiconductor material between and in contact with the two electrodes, a layer of liquid crystal material in contact with and on said semiconductor body, and a third electrode in contact with the layer of liquid crystal material. Integrated optologic devices are made from these liquid crystal transistors.

Abstract: A liquid crystal device includes a liquid crystal material encapsulated between two glass plates having electrodes on their inner surfaces. An illuminator is provided across the back of the liquid crystal device. The illuminator includes a radioactive material encapsulated between two glass plates. The inner surface of the illuminator plates are coated with a cathodoluminescent phosphor. One of the plates of the illuminator may be one of the plates of the liquid crystal device. The photons from the phosphor of the illuminator illuminate the liquid crystal device.