Abstract: A system on a chip (SoC) includes a first subsystem, a second subsystem and a compression block connected to the first and second subsystems, wherein the compression block includes a decoder and an encoder. The compression block receives spill data generated by a compute element in one of the first and second subsystems, compresses the spill data using the encoder and stores the compressed spill data in a data block in local memory of one of the compute elements.

Abstract: In an embodiment, a system includes a buffer configured to store a plurality of pixel blocks of an image, a first processor unit configured to receive a pixel block of the of the plurality of pixel blocks and select whether to separately encode or jointly encode pixel components of the pixel block by computing eigenvalues for the pixel components, a second processor unit configured to compute, responsive to the first processing unit selecting to jointly encode the pixel block, (i) an eigenvector for the pixel components of the pixel block based on the eigenvalues and (ii) endpoints on the eigenvector for encoding the pixel components, an encoder unit configured to encode, responsive to the first processing unit selecting to jointly encode the pixel block, the pixel components of the pixel block jointly based on the eigenvector and the endpoints.

Abstract: In one embodiment, a computing system may access color components of a pixel region in an image, and then determine a color variance for each of the color components. The computing system may further determine a desired bit allocation for each of the color components based on the color variance associated with that color component. The computing system may then determine a total bit allocation for the pixel region based on the desired bit allocations for the color components, as well as a number of unallocated bits available for allocation. The computing system may further determine a final bit allocation for each of the color components by allocating the total bit allocation to each of the color components according to the desired bit allocation for each of the color components. The computing system may then encode each of the color components using the associated final bit allocation.

Abstract: In an embodiment, a method involves accessing a first pixel block of an image, the first pixel block comprising pixels, each associated with multiple pixel components, determining whether to separately or jointly encode the multiple pixel components of each of the pixels of the first pixel block, determining that the multiple pixel components of each of the pixels in the first pixel block are to be jointly encoded based on (1) determining, based on the multiple pixel components of each of the pixels, a line defined within a three-dimensional coordinate system in which each of the pixels is represented as a three-dimensional point and (2) determining that the line satisfies a predetermined criteria, and encoding the multiple pixel components of each of the pixels in the first pixel block as a single quantized value based on a projection of the three-dimensional point associated with that pixel onto the line.

Abstract: A computing system may access first alpha values associated with first pixels in a first pixel region of an image and determine a bit budget for encoding the first alpha values. The computing system may then select a first alpha-encoding mode for the first alpha values to reflect a determination that the first alpha values are all fully transparent or all fully opaque, and encode the first alpha values by storing the selected first alpha-encoding mode as part of a metadata without using the bit budget to encode the first alpha values individually. The computing system may then update a record of unallocated bits available for allocation based on the bit budget unused in the encoding of the first alpha values, and allocate, based on the record of unallocated bits, bits to encode a set of alpha values different from the first alpha values.

Abstract: In one embodiment, a computing system may access first alpha values associated with first pixels in a first pixel region of an image and determine a bit budget for encoding the first alpha values. The computing system may then select a first alpha-encoding mode for the first alpha values to reflect a determination that the first alpha values are all fully transparent or all fully opaque, and encode the first alpha values by storing the selected first alpha-encoding mode as part of a metadata without using the bit budget to encode the first alpha values individually. The computing system may then update a record of unallocated bits available for allocation based on the bit budget unused in the encoding of the first alpha values, and allocate, based on the record of unallocated bits, bits to encode a set of alpha values different from the first alpha values.

Abstract: Disclosed herein includes a system, a method, and a device for compressing image data. The device includes one or more processors, coupled to memory, configured to identify a plurality of sub-blocks of a block of image data including a first sub-block and a second sub-block. The one or more processors are configured to identify a first data characteristic of data of the first sub-block and a second data characteristic of data of the second sub-block, determine a first compression technique based at least on the first data characteristic of the first sub-block, determine a second compression technique based at least on the second data characteristic of the second sub-block, and compress the first sub-block using the first compression technique and the second sub-block using the second compression technique.

Abstract: This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

Abstract: In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The first control unit may be configured to obtain, from the second control unit, a first memory address associated with a data reading process of the second processing unit, receive a write request from the first processing unit, the read request having an associated second memory address, and write data into the memory region based on the write request in response to a determination that the second memory address falls outside of the guarded reading region.

Abstract: In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.

Abstract: In one embodiment, one or more computing systems may determine a first display content to be displayed on a display. The first display content may be associated with one or more frames. The one or more computing systems may determine an optimization operation for the first display content based on one or more first parameters associated with the display or one or more second parameters associated with the one or more frames. The one or more computing systems may adjust the one or more frames based on the optimization operation. The adjusted one or more frames may have at least one optimized attribute comparing to the one or more frames before being adjusted. The one or more computing systems may output the adjusted one or more frames to the display to represent the first display content.

Abstract: Disclosed herein includes a system, a method, and a device for compressing image data. The device includes one or more processors, coupled to memory, configured to identify a plurality of sub-blocks of a block of image data including a first sub-block and a second sub-block. The one or more processors are configured to identify a first data characteristic of data of the first sub-block and a second data characteristic of data of the second sub-block, determine a first compression technique based at least on the first data characteristic of the first sub-block, determine a second compression technique based at least on the second data characteristic of the second sub-block, and compress the first sub-block using the first compression technique and the second sub-block using the second compression technique.

Abstract: In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.

Abstract: In an embodiment, a method involves temporarily storing, by each of multiple slots of a ring buffer, a pixel block of multiple pixels blocks of an image until the pixel block is encoded, performing, by multiple processor units connected in series, different encoding operations in an encoding pipeline, each processor unit configured to selectively access the pixel block from a slot of the multiple slots to determine characteristics of the accessed pixel block, wherein the multiple processing units are configured to sequentially obtain access to a slot of the multiple slots and concurrently process the pixel blocks stored in different ones of the multiple slots, and selectively accessing and encoding, by an encoder unit, the pixel block stored in a slot of the multiple slots based on the characteristics of the pixel block determined by the multiple processing units.

Abstract: In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The first control unit may be configured to obtain, from the second control unit, a first memory address associated with a data reading process of the second processing unit, receive a write request from the first processing unit, the read request having an associated second memory address, and write data into the memory region based on the write request in response to a determination that the second memory address falls outside of the guarded reading region.

Abstract: In an embodiment, a method involves accessing a first pixel block of an image, the first pixel block comprising pixels, each associated with multiple pixel components, determining whether to separately or jointly encode the multiple pixel components of each of the pixels of the first pixel block, determining that the multiple pixel components of each of the pixels in the first pixel block are to be jointly encoded based on (1) determining, based on the multiple pixel components of each of the pixels, a line defined within a three-dimensional coordinate system in which each of the pixels is represented as a three-dimensional point and (2) determining that the line satisfies a predetermined criteria, and encoding the multiple pixel components of each of the pixels in the first pixel block as a single quantized value based on a projection of the three-dimensional point associated with that pixel onto the line.

Abstract: In one embodiment, a computing system may determine a quantization range having a first quantization endpoint and a second quantization endpoint. While fixing the second quantization endpoint to an initial value determined based on the color range, one of a plurality of first candidate values for the first quantization endpoint is selected based on a plurality of corresponding first quantization errors. While fixing the first quantization endpoint to the selected first candidate value, one of a plurality of second candidate values for the second quantization endpoint is selected based on a plurality of corresponding second quantization errors. The computing system may define quantization levels corresponding to the bit depth using the quantization range defined by the first quantization endpoint and the second quantization endpoint, and then encode the one or more color components of the pixel region using the quantization levels.

Abstract: In an embodiment, a method involves accessing a first pixel block of an image, the first pixel block comprising pixels, each associated with three color values, determining whether to separately or jointly encode the three color values of each of the pixels of the first pixel block, determining that the three color values of each of the pixels in the first pixel block are to be jointly encoded based on (1) determining, based on the three color values of each of the pixels, a line defined within a three-dimensional coordinate system in which each of the pixels is represented as a three-dimensional point and (2) determining that the line satisfies a predetermined criteria, and encoding the three color values of each of the pixels in the first pixel block as a single quantized value based on a projection of the three-dimensional point associated with that pixel onto the line.

Abstract: In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The second control unit may be configured to obtain, from the first control unit, a first memory address associated with a data writing process of the first processing unit, receive a read request from the second processing unit, the read request having an associated second memory address, and delay execution of the read request based on a comparison of the first memory address and the second memory address.

Abstract: In one embodiment, a computing system may access color components of a pixel region in an image, and then determine a color variance for each of the color components. The computing system may further determine a desired bit allocation for each of the color components based on the color variance associated with that color component. The computing system may then determine a total bit allocation for the pixel region based on the desired bit allocations for the color components, as well as a number of unallocated bits available for allocation. The computing system may further determine a final bit allocation for each of the color components by allocating the total bit allocation to each of the color components according to the desired bit allocation for each of the color components. The computing system may then encode each of the color components using the associated final bit allocation.