Patents by Inventor Lawrence A. P. Chisvin

Lawrence A. P. Chisvin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory subsystem command input queue having status locations for resolving conflicts
    Patent number: 5388222
    Abstract: Methodology and circuitry for managing read and write commands from nodes to a shared memory resource on a common data bus, including nodes with write-back caches, nodes with write-through caches and nodes without caches.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: February 7, 1995
    Assignee: Digital Equipment Corporation
    Inventors: Lawrence A. P. Chisvin, John K. Grooms, Joseph F. Rantala, David W. Hartwell
  • Method and apparatus for capturing real-time data bus cycles in a data processing system
    Patent number: 5276809
    Abstract: A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: January 4, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Lawrence A. P. Chisvin, John K. Grooms, Richard L. Sites, Donald W. Smelser