Abstract: An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.

Abstract: A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Abstract: An optical system for aligning various avionics sensors and displays includes an aircraft having a nose section, a forward fuselage section, and an aft fuselage section, and at least one of a sensor, a display, a sensor substitute, and a display substitute. A laser is attached to a side of the aft section of the fuselage, and is directed toward a corresponding laser target on a laser target board. The laser target board is mounted on a frame and is positioned a distance away from the aircraft, and includes a plurality of laser targets. Between the laser target board and the laser is a reference plate which includes an aperture through which a beam from the laser passes. With the laser aligned with its respective laser target, the relative position of the sensor, display, sensor substitute, or display substitute is determined relative to known positions on the aircraft.

Abstract: An interconnect structure for an integrated circuit includes a plurality of first-type interconnect elements and a second-type of interconnect element which directly contact an underlying first-type interconnect element. The second-type interconnect element extends along a first axis to define a horizontal length and along a second axis to define a vertical height. The second-type interconnect element and the first-type interconnect element define a conductive via comprising a metal material extending continuously along the second axis from a base of the underlying first-type interconnect element and stopping at the upper surface of the second-type interconnect element. The vertical height of the second-type interconnect element is greater than the vertical height of the first-type interconnect elements.

Abstract: A hydrocarbon fluid containment article having a wall with a surface that is wetted by hydrocarbon fluid. The surface includes an anti-coking coating. The anti-coking coating includes a copper salt, a silver salt, or a combination thereof. A gas turbine engine component including a wall having a first surface and an anti-coking coating on the first surface of the wall that is wetted by hydrocarbon fluid. The anti-coking coating including a copper salt, a silver salt, or a combination thereof that prevents the formation of gum or coke on a surface thereon. Methods for reducing the deposition of thermal decomposition products on a wall of an article are also provided.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring, a second level of interconnect wiring disposed above the first level of interconnect wiring, a third level of interconnect wiring disposed above the second level of interconnect wiring, and a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. A contact area between the sidewall of the skip via and the second level of interconnect wiring is greater than a contact area between a bottom portion of the skip via and a top portion of the first level of interconnect wiring.

Abstract: A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.

Abstract: A semiconductor structure comprises a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.

Abstract: A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.

Abstract: Semiconductor device and methods of forming the same include a semiconductor channel. A top source/drain structure is on the semiconductor channel. A bottom source/drain structure is under the semiconductor channel. The bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: A semiconductor chip device includes a substrate with a first dielectric material of a first permittivity value. A power input line and ground line are positioned in the substrate and arranged to form a decoupling capacitor. A region of the substrate in between the power input line and the ground line is doped with a second dielectric material of a second permittivity value that is higher than the first permittivity value. The region doped with the second dielectric material lacks a signal body. By incorporating a region with higher permittivity, in what is generally unused space for power delivery, the region becomes a decoupling capacitor for nearby power delivery elements. By adding decoupling capacitance to the previously unused space, noise in a circuit is more easily controlled and the chip device becomes more reliable.

Abstract: A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.

Abstract: An interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer.

Abstract: A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Abstract: A feature-rich, improved vehicle traffic signal control system that uses network technology is provided herein. For example, the improved vehicle traffic signal control system may include a control box and light heads that include processors. The control box in the improved vehicle traffic signal control system may include fewer components and/or fewer wires extending therefrom as compared to a typical control box. In particular, the control box in the improved vehicle traffic signal control system may not include relays, a conflict monitor, or other similar components. Rather, the improved control box may simply include a controller that is coupled to various light heads via Ethernet cables. The Ethernet cables can carry electrical power, thereby providing power to the light heads. The light head processors can use network technology to control light activation, to perform conflict monitoring, to receive data from various sensors to adjust traffic flow, etc.

Abstract: A semiconductor device and formation thereof. The semiconductor device includes a first via in a metal layer, wherein the first via is a single damascene structure. The semiconductor device further includes a second via in the metal level, wherein the second via is a dual damascene structure.

Abstract: A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.

Abstract: An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.