Abstract: A general-purpose, adaptable, device for interfacing acoustic and ultrasonic transducers to circuits for high resolution distance and motion measurement, and two-way communication. A generator signal (52) synchronizes to a sensing transducer signal (21), or a reference signal (23). A detector (20) provides a detected-cycle signal (22) and a detected-amplitude signal (24) from the signal being detected. Comparator (30) creates a comparator signal (32) from the detected-cycle and generator signals. A sustaining circuit provides flywheel operation during gaps. A driver (60) drives a radiating transducer. Options include: single or dual transducer operation, continuous or pulsed-burst operation, optimum frequency communication using low cost piezoelectric transducers, sonic wave frequency scanning, phase and amplitude modulation and demodulation, fast synchronization, detected vs reference signal comparison, and self-testing.

Abstract: A method and apparatus for measuring aggregate bit shift (peak shift) timing error in the readback signal of a magnetic storage system. The method provides an effective measure of the relative goodness of one magnetic head with respect to another magnetic head. A repetitive data pattern is written onto a magnetic disk. The magnetic head under test reads back the magnetic transitions from the disk. The signals are amplified, detected and digitized. A low cost gating system synchronizes to the recorded data pattern and outputs a pulse at the beginning and end of a selected period corresponding to two transitions in the data pattern. A time interval measuring device connected at the output of the gating system determines the average time or time variance between the beginning and end data pulses. The average time value correlates to the aggregate bit shift inherent in the magnetic read head being measured. This relatively simple system provides fast, low cost, accurate bit shift measurement.

Abstract: A dual loop phase locked oscillator system comprises a pair of phase locked oscillators coupled with priority logic gates for selectively operating each oscillator. During a lock-to-data mode, the logic gates are operated so that one of the oscillators is operated by the input data to lock to the data rate, while the other oscillator is operated by the output of the first oscillator to also lock to the data rate. During a normal mode, or coasting mode (when no data is present), each oscillator operates off the output of the other to thereby maintain oscillation at the data rate. Thus, the oscillators are selectively operated in tandem or in parallel.