Abstract: Embodiments of the invention address deficiencies of the art in respect to power sequencing, and provide a method, system and computer program product for supporting coupling with independent logic circuits. In one embodiment of the invention, a computer system supporting coupling with independent logic circuits may include an independent logic circuit including at least one voltage regulator that regulates voltage to core logic such that voltage is transferred to the core logic upon receiving a first level of voltage. The independent logic circuit may further include an I/O driver that becomes operational upon receiving a highest level of voltage higher than the first level of voltage. The computer system may further include a voltage ramp for transferring voltage to the independent logic circuit at the first level voltage for a predetermined period of time and subsequently at the highest level of voltage.

Abstract: A method of operating a delay circuit to impose a selected delay on an electronic signal the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.

Abstract: A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.