Abstract: A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path.

Abstract: A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets.

Abstract: An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

Abstract: Swapping of bits between different words of a memory is accomplished by a single permutation means. The single permutation means generates actual address bits for all the bit positions in a memory word. These actual address bits are in a local store. Each time a memory word is accessing the locations of the bits are substituted for logical address bits and fed to the decoders of the different bit positions in the memory word being accessed.

Abstract: A method of operating a large fault tolerant semiconductor memory is described which increases the probability that data words read from memory will not contain uncorrectable errors. The method involves storing a data word at a location in memory that may have a defect in either the true form or compliment form depending on which form will be perceived by an error correcting system as containing no errors on readout. Each data word transferred to memory is tested to see if one form or the other results in an error on readout. If the true form results in an error indication, the data portion of the word is stored in compliment form and the check byte stored in true form.On a subsequent transfer of the word from memory, the ECC system indicates an apparent uncorrectable error resulting from both portions of the word being stored in a different form while in fact the uncorrectable error indication is a signal that the data portion was stored in compliment form.