Patents by Inventor Lawrence Lai
Lawrence Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130265842Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.Type: ApplicationFiled: May 23, 2013Publication date: October 10, 2013Inventors: Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai
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Patent number: 8432766Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: GrantFiled: March 1, 2012Date of Patent: April 30, 2013Assignee: RAMBUS Inc.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Patent number: 8391099Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: GrantFiled: May 9, 2011Date of Patent: March 5, 2013Assignee: Rambus Inc.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Patent number: 8271747Abstract: An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block.Type: GrantFiled: June 29, 2009Date of Patent: September 18, 2012Assignee: Rambus Inc.Inventor: Lawrence Lai
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Publication number: 20120170399Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: ApplicationFiled: March 1, 2012Publication date: July 5, 2012Applicant: RAMBUS INC.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Patent number: 8190808Abstract: A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.Type: GrantFiled: August 17, 2004Date of Patent: May 29, 2012Assignee: Rambus Inc.Inventors: Lawrence Lai, Wayne S. Richardson, Chad A. Bellows
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Publication number: 20120117317Abstract: In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command.Type: ApplicationFiled: June 17, 2010Publication date: May 10, 2012Applicant: RAMBUS Inc.Inventors: Thomas Sheffler, Lawrence Lai, Liang Peng, Bohuslav Rychlik
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Patent number: 8154947Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: GrantFiled: September 22, 2011Date of Patent: April 10, 2012Assignee: RAMBUS Inc.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Publication number: 20120020178Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: ApplicationFiled: September 22, 2011Publication date: January 26, 2012Applicant: RAMBUS INC.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Patent number: 8050134Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: GrantFiled: February 2, 2011Date of Patent: November 1, 2011Assignee: RAMBUS Inc.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Publication number: 20110211415Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: ApplicationFiled: May 9, 2011Publication date: September 1, 2011Applicant: RAMBUS INC.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Publication number: 20110153932Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: ApplicationFiled: February 2, 2011Publication date: June 23, 2011Applicant: RAMBUS INC.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Patent number: 7940598Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: GrantFiled: July 22, 2008Date of Patent: May 10, 2011Assignee: Rambus Inc.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Patent number: 7907470Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: GrantFiled: February 24, 2009Date of Patent: March 15, 2011Assignee: RAMBUS Inc.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Publication number: 20100030955Abstract: An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block.Type: ApplicationFiled: June 29, 2009Publication date: February 4, 2010Applicant: RAMBUS, INC.Inventor: Lawrence Lai
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Publication number: 20090193202Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: ApplicationFiled: February 24, 2009Publication date: July 30, 2009Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Patent number: 7505356Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: GrantFiled: September 11, 2007Date of Patent: March 17, 2009Assignee: Rambus Inc.Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
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Publication number: 20080279032Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: ApplicationFiled: July 22, 2008Publication date: November 13, 2008Applicant: RAMBUS INC.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Patent number: 7420874Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: GrantFiled: April 6, 2005Date of Patent: September 2, 2008Assignee: Rambus Inc.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Publication number: 20080062807Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.Type: ApplicationFiled: September 11, 2007Publication date: March 13, 2008Inventors: Frederick Ware, Lawrence Lai, Chad Bellows, Wayne Richardson