Abstract: In an embodiment, a System-on-Chip (SoC) may include: a plurality of core domains, and a memory coupled to the plurality of core domains through a hardware firewall, wherein the hardware firewall is configured to enforce an adaptive Deny-By-Default (DBD) access policy in response to an event. In another embodiment, a circuit, may include: an access control policy generator configured to produce an adaptive DBD policy, and a hardware firewall coupled to the access control policy generator, the hardware firewall configured to enforce the adaptive DBD policy. In yet another embodiment, a method may include: storing an indication of a first DBD configuration state, the first DBD configuration state usable to enforce a first DBD access control policy, and changing the stored indication to a second DBD configuration state, the second DBD configuration state usable to enforce a second DBD access control policy.

Abstract: A data processing system includes a plurality of subsystems, a plurality of local security controllers, and a central security controller. Each subsystem of the plurality of subsystems has a security component for providing a security function. A local security controller corresponds to each one of the subsystems. Each local security controller ensures compliance of the security component with local security policies of the subsystem to which the local security controller corresponds. The central security controller is coupled to the local security controller of each of the plurality of subsystems. The central security controller ensures data processing system compliance with system wide security policies. In the event of a detected security violation, the local security controller may respond automatically, without involvement of the central security controller. A method for securing the data processing system is also provided.

Abstract: A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.

Abstract: A data processing system includes a plurality of subsystems, a plurality of local security controllers, and a central security controller. Each subsystem of the plurality of subsystems has a security component for providing a security function. A local security controller corresponds to each one of the subsystems. Each local security controller ensures compliance of the security component with local security policies of the subsystem to which the local security controller corresponds. The central security controller is coupled to the local security controller of each of the plurality of subsystems. The central security controller ensures data processing system compliance with system wide security policies. In the event of a detected security violation, the local security controller may respond automatically, without involvement of the central security controller. A method for securing the data processing system is also provided.

Abstract: A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.

Abstract: A runtime security system, including: a shared core configured to execute processes having varying levels of trustworthiness configured to receive security services requests; an execution monitor configured to monitor the execution of the shared core further comprising a timer, a policy table, and an execution monitor state machine; secure assets including cryptographic keys; and immutable security service functions configured to enable access to the secure assets in response to secure services requests; wherein the execution monitor is configured to: detect that the shared core has received a secure boot request; verify that the secure boot request is valid; allow the shared core to securely boot when the secure boot request valid.

Abstract: A runtime security system, including: a shared core configured to execute processes having varying levels of trustworthiness configured to receive security services requests; an execution monitor configured to monitor the execution of the shared core further comprising a timer, a policy table, and an execution monitor state machine; secure assets including cryptographic keys; and immutable security service functions configured to enable access to the secure assets in response to secure services requests; wherein the execution monitor is configured to: detect that the shared core has received a secure boot request; verify that the secure boot request is valid; allow the shared core to securely boot when the secure boot request valid.

Abstract: A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.