Abstract: Embodiments of the present invention provide systems and methods to enable secure communication between a host processor and external real time counter (RTC) logic. In an embodiment, the host processor generates a message including a command to an external device containing the RTC. The external device verifies a Message Authentication Code (MAC) included in the message and responds to the command. Embodiments of the present invention advantageously provide a dedicated power domain for the external RTC logic while guarding against third party attacks on the RTC logic and the communication between the RTC logic and the host processor.

Abstract: Certain aspects of a method and system for handling signals in a communication system are disclosed. Aspects of one method may include processing, within a single chip, any one of a plurality of wireless access communication protocols by any one of a plurality of on-chip baseband processors. None of the on-chip baseband processors is a dedicated processor that is configured to handle only a single wireless access communication protocol. The plurality of wireless access communication protocols may comprise WCDMA, HSDPA, GSM, GPRS, and EDGE. Any one of the plurality of on-chip baseband processors may be configured to process any one of the plurality of wireless access communication protocols.

Abstract: A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed.