Patents by Inventor Lawrence R. Fraley
Lawrence R. Fraley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7665207Abstract: A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.Type: GrantFiled: June 19, 2006Date of Patent: February 23, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya Markovich
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Patent number: 7161810Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.Type: GrantFiled: September 30, 2005Date of Patent: January 9, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya Markovich
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Patent number: 7035113Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.Type: GrantFiled: March 24, 2003Date of Patent: April 25, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya R. Markovich
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Patent number: 7023707Abstract: An information handling system, e.g., computer, server or mainframe, which includes a multi-chip electronic package utilizing an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities of the final system product.Type: GrantFiled: March 24, 2003Date of Patent: April 4, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya R. Markovich
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Patent number: 6992896Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.Type: GrantFiled: September 15, 2003Date of Patent: January 31, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya Markovich
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Publication number: 20040150114Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.Type: ApplicationFiled: March 24, 2003Publication date: August 5, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya R. Markovich
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Publication number: 20040150095Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.Type: ApplicationFiled: September 15, 2003Publication date: August 5, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya Markovich
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Publication number: 20040150101Abstract: An information handling system, e.g., computer, server or mainframe, which includes a multi-chip electronic package utilizing an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities of the final system product.Type: ApplicationFiled: March 24, 2003Publication date: August 5, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya R. Markovich
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Patent number: 4545000Abstract: An improved projection lamp unit including a glass reflector having a concave reflecting surface and a tungsten halogen lamp positioned within the concavity of the reflector. The concave reflecting surface of the reflector is provided with alternately disposed radially extending regions including a series of specular stripes in combination with alternately spaced regions of facets. Preferably four or five stripes and an associated four or five facet regions are provided.Type: GrantFiled: March 25, 1985Date of Patent: October 1, 1985Assignee: GTE Products CorporationInventors: Lawrence R. Fraley, Arnold E. Westlund, Jr.
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Patent number: 4229161Abstract: An electrically-activated photoflash lamp which includes a thin member (e.g. a mica disk) therein located between the lamp's combustible shreds and primer material. The disk prevents the shreds from contacting the primer material and any portions of the lamp's electrical conductors which have access to the interior of the envelope. A method of making the lamp is also provided.Type: GrantFiled: January 2, 1979Date of Patent: October 21, 1980Assignee: GTE Products CorporationInventors: Andre C. Bouchard, Lawrence R. Fraley
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Patent number: 4161388Abstract: A flashlamp signal device which includes an illumination means for providing a prolonged, visible signal after actuation of each of the device's flashlamps. The illumination means may be in the form of a phosphor coating within the device or on an adjacent, movable panel, or the phosphor may be impregnated within the light-transmitting housing or support structure of the device.Type: GrantFiled: March 17, 1977Date of Patent: July 17, 1979Assignee: GTE Sylvania IncorporatedInventors: Andre C. Bouchard, Lawrence R. Fraley
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Patent number: D281355Type: GrantFiled: October 3, 1983Date of Patent: November 12, 1985Assignee: GTE Products CorporationInventors: Lawrence R. Fraley, Arnold E. Westlund, Jr.