Patents by Inventor Lawrence Rogel
Lawrence Rogel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9201674Abstract: One embodiment of the present invention is a method of migrating functionality to a target virtualized mobile device including virtualization software that supports one or more virtual machines, the method including: (a) embodying the functionality in a virtual machine; and (b) migrating the virtual machine to the target virtualized mobile device.Type: GrantFiled: May 7, 2013Date of Patent: December 1, 2015Assignee: VMware, Inc.Inventors: Lawrence Rogel, Scott W. Devine
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Publication number: 20130254369Abstract: One embodiment of the present invention is a method of migrating functionality to a target virtualized mobile device including virtualization software that supports one or more virtual machines, the method including: (a) embodying the functionality in a virtual machine; and (b) migrating the virtual machine to the target virtualized mobile device.Type: ApplicationFiled: May 7, 2013Publication date: September 26, 2013Applicant: VMware, Inc.Inventors: Lawrence ROGEL, Scott W. DEVINE
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Patent number: 7392352Abstract: A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.Type: GrantFiled: July 7, 2005Date of Patent: June 24, 2008Assignee: Massachusetts Institute of TechnologyInventors: Arvind Mithal, Xiaowei Shen, Lawrence Rogel
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Publication number: 20060004967Abstract: A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.Type: ApplicationFiled: July 7, 2005Publication date: January 5, 2006Inventors: Arvind Mithal, Xiaowei Shen, Lawrence Rogel
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Patent number: 6757787Abstract: A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory.Type: GrantFiled: December 19, 2002Date of Patent: June 29, 2004Assignee: Massachusetts Institute of TechnologyInventors: Xiaowei Shen, Arvind Mithal, Lawrence Rogel
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Publication number: 20040093467Abstract: A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory.Type: ApplicationFiled: December 19, 2002Publication date: May 13, 2004Applicant: Massachusetts Institute of Technology, a Massachusetts corporationInventors: Xiaowei Shen, Arvind Mithal, Lawrence Rogel
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Publication number: 20040083343Abstract: A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.Type: ApplicationFiled: October 21, 2003Publication date: April 29, 2004Applicant: Massachusetts Institute of Technology, a Massachusetts corporationInventors: Arvind Mithal, Xiaowei Shen, Lawrence Rogel
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Patent number: 6636950Abstract: A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.Type: GrantFiled: April 27, 1999Date of Patent: October 21, 2003Assignee: Massachusetts Institute of TechnologyInventors: Arvind Mithal, Xiaowei Shen, Lawrence Rogel
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Patent number: 6526481Abstract: A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory.Type: GrantFiled: April 27, 2000Date of Patent: February 25, 2003Assignee: Massachusetts Institute of TechnologyInventors: Xiaowei Shen, Arvind Mithal, Lawrence Rogel