Abstract: An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.

Abstract: An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: A first phase alignment circuit generates an indication of a phase of a first clock signal. A second phase alignment circuit adjusts a phase of a second clock signal based on a data signal. The second phase alignment circuit adjusts the phase of the second clock signal based on the indication of the phase of the first clock signal. The second phase alignment circuit resets an indication of the phase of the second clock signal generated based on the data signal in response to the indication of the phase of the first clock signal. The second phase alignment circuit captures a value of the data signal in response to the second clock signal.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.