Patents by Inventor Layachi Daineche
Layachi Daineche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11269986Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.Type: GrantFiled: October 22, 2019Date of Patent: March 8, 2022Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SASInventors: Vincent Berthelot, Layachi Daineche
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Patent number: 11143701Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.Type: GrantFiled: June 23, 2020Date of Patent: October 12, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
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Patent number: 11144678Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.Type: GrantFiled: March 8, 2018Date of Patent: October 12, 2021Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda, Layachi Daineche
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Patent number: 11055237Abstract: In a non-volatile memory of a microcontroller, first information representative of a value selected among at least four values is stored. Furthermore, for each of a plurality of areas of the memory, second information representative of a type selected among two types is also stored. Access to each of the areas is conditioned according to the selected value and to the type of the area.Type: GrantFiled: October 7, 2019Date of Patent: July 6, 2021Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SASInventors: Layachi Daineche, Xavier Chbani, Nadia Van-Den-Bossche
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Publication number: 20200319247Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
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Patent number: 10705141Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.Type: GrantFiled: October 10, 2018Date of Patent: July 7, 2020Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
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Publication number: 20200134164Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.Type: ApplicationFiled: October 22, 2019Publication date: April 30, 2020Applicants: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SASInventors: Vincent BERTHELOT, Layachi DAINECHE
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Publication number: 20200110713Abstract: In a non-volatile memory of a microcontroller, first information representative of a value selected among at least four values is stored. Furthermore, for each of a plurality of areas of the memory, second information representative of a type selected among two types is also stored. Access to each of the areas is conditioned according to the selected value and to the type of the area.Type: ApplicationFiled: October 7, 2019Publication date: April 9, 2020Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SASInventors: Layachi DAINECHE, Xavier CHBANI, Nadia VAN-DEN-BOSSCHE
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Publication number: 20190107576Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.Type: ApplicationFiled: October 10, 2018Publication date: April 11, 2019Inventors: Lionel Sinegre, Eric Sagnard, Stephan Courcambeck, William Orlando, Layachi Daineche
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Publication number: 20180260585Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.Type: ApplicationFiled: March 8, 2018Publication date: September 13, 2018Inventors: Mirko DONDINI, Gaetano DI STEFANO, Sergio ABENDA, Layachi DAINECHE
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Patent number: 7818654Abstract: There is provided an addressing architecture for parallel processing of recursive data. A basic idea is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. This is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.Type: GrantFiled: June 20, 2005Date of Patent: October 19, 2010Assignee: ST-Ericsson SAInventors: Christine Schenone, Layachi Daineche, Aritz Sanchez Lekue
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Publication number: 20080192865Abstract: The present invention relates to an addressing architecture for parallel processing of recursive data. A basic idea of the present invention is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. The present invention is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.Type: ApplicationFiled: June 20, 2005Publication date: August 14, 2008Applicant: Koninklijke Philips Electronics N.V.Inventors: Christine Schenone, Layachi Daineche, Aritz Sanchez Lekue