Patents by Inventor Layne Bunker
Layne Bunker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10629502Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: GrantFiled: July 6, 2018Date of Patent: April 21, 2020Assignee: Micron Technology, Inc.Inventors: Ebrahim H Hargan, Layne Bunker, Dragos Dimitriu, Gregory A. King
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Publication number: 20190109057Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: ApplicationFiled: July 6, 2018Publication date: April 11, 2019Inventors: Ebrahim H. Hargan, Layne Bunker, Dragos Dimitriu, Gregory A. King
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Patent number: 10037926Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: GrantFiled: April 18, 2016Date of Patent: July 31, 2018Assignee: Micron Technology, Inc.Inventors: Ebrahim H Hargan, Layne Bunker, Dragos Dimitriu, Gregory A. King
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Publication number: 20160233136Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: ApplicationFiled: April 18, 2016Publication date: August 11, 2016Inventors: Ebrahim H. Hargan, Layne Bunker, Dragos Dimitriu, Gregory A. King
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Patent number: 9318394Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: GrantFiled: September 23, 2014Date of Patent: April 19, 2016Assignee: Micron Technology, Inc.Inventors: Ebrahim H Hargan, Layne Bunker, Dragos Dimitriu, Gregory A. King
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Publication number: 20150008953Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: ApplicationFiled: September 23, 2014Publication date: January 8, 2015Inventors: Ebrahim H. Hargan, Layne Bunker, Dragos Dimitriu, Gregory A. King
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Patent number: 8847619Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: GrantFiled: July 8, 2011Date of Patent: September 30, 2014Assignee: Micron Technology, Inc.Inventors: Ebrahim H Hargan, Layne Bunker, Dragos Dimitriu, Gregory King
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Publication number: 20110267092Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Inventors: Ebrahim H. Hargan, Layne Bunker, Dragos Dimitriu, Gregory King
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Patent number: 8023350Abstract: A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.Type: GrantFiled: July 12, 2010Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventors: Layne Bunker, Ebrahim Hargan
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Patent number: 7977962Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: GrantFiled: July 15, 2008Date of Patent: July 12, 2011Assignee: Micron Technology, Inc.Inventors: Ebrahim H Hargan, Layne Bunker, Dragos Dimitriu, Gregory King
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Publication number: 20100271896Abstract: A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.Type: ApplicationFiled: July 12, 2010Publication date: October 28, 2010Applicant: Micron Technology, Inc.Inventors: Layne Bunker, Ebrahim Hargan
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Patent number: 7773441Abstract: A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.Type: GrantFiled: June 18, 2008Date of Patent: August 10, 2010Assignee: Micron Technology, Inc.Inventors: Layne Bunker, Ebrahim Hargan
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Publication number: 20100013512Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.Type: ApplicationFiled: July 15, 2008Publication date: January 21, 2010Inventors: Ebrahim H. Hargan, Layne Bunker, Dragos Dimitriu, Gregory King
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Publication number: 20090316501Abstract: A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.Type: ApplicationFiled: June 18, 2008Publication date: December 24, 2009Applicant: Micron Technology, Inc.Inventors: Layne Bunker, Ebrahim Hargan
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Publication number: 20070152743Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: March 7, 2007Publication date: July 5, 2007Inventors: Brent Keeth, Layne Bunker, Raymond Beffa, Frank Ross
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Publication number: 20070008811Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: June 14, 2006Publication date: January 11, 2007Inventors: Brent Keeth, Layne Bunker, Raymond Beffa, Frank Ross
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Publication number: 20070008794Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: June 14, 2006Publication date: January 11, 2007Inventors: Brent Keeth, Layne Bunker, Raymond Beffa, Frank Ross
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Patent number: 6034900Abstract: An architecture for a wide data path in a memory device formed in a semiconductor substrate includes an array of memory cells is formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns. A plurality of complementary pairs of digit lines are formed in the array region from a first conductive layer, each complementary pair being coupled to a plurality of memory cells in an associated column. A plurality of word lines are formed in the array region from a second conductive layer, each word line being coupled to each memory cell in an associated row. A plurality of sense amplifiers are formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier being coupled to an associated pair of complementary digit lines. A plurality of input/output lines are disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers.Type: GrantFiled: September 2, 1998Date of Patent: March 7, 2000Assignee: Micron Technology, Inc.Inventors: Brian Shirley, Layne Bunker
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Patent number: RE38955Abstract: An architecture for a wide data path in a memory device formed in a semiconductor substrate includes an array of memory cells is formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns. A plurality of complementary pairs of digit lines are formed in the array region from a first conductive layer, each complementary pair being coupled to a plurality of memory cells in an associated column. A plurality of word lines are formed in the array region from a second conductive layer, each word line being coupled to each memory cell in an associated row. A plurality of sense amplifiers are formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier being coupled to an associated pair of complementary digit lines. A plurality of input/output lines are disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers.Type: GrantFiled: March 7, 2002Date of Patent: January 31, 2006Assignee: Micron Technology, Inc.Inventors: Brian Shirley, Layne Bunker
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Patent number: RE38109Abstract: A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to receive respective data signals, and a plurality of array groups each including a plurality of arrays and each array includes a plurality of memory cells. A plurality of input/output line groups each include a plurality of input/output lines coupled to the arrays of an associated array group. The block write circuit comprises a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective data lines in an associated data line group. Each write driver circuit includes an input and develops a data signal on its output responsive to a data signal applied on its input. A multiplexer circuit includes a plurality of inputs coupled to respective data terminals, and a plurality of output subgroups.Type: GrantFiled: December 20, 2001Date of Patent: May 6, 2003Assignee: Micron Technology, Inc.Inventors: Todd A. Merritt, Layne Bunker