Abstract: A method of rapid non-data aided carrier signal acquisition for a low symbol rate carrier signal, comprising receiving and converting an analog intermediate frequency carrier to a digital carrier signal, down-converting the signal to substantially baseband, reducing a sampling rate of the digital carrier signal using a decimation filter, determining a highest Fast Fourier Transform (FFT) based on a result of one or more FFT's generated by an FFT module using a peak finder, selecting an input source for the FFT module using a multiplexer, generating a frequency estimate of the digital carrier signal using a walking coarse detector, tuning a carrier recovery loop (CRL) based on the frequency estimate generated by the walking coarse detector, determining a final carrier frequency offset estimate using a result of the FFT module, modulation removal, and the peak finder, and programming an oscillator within the CRL to the final carrier frequency offset estimate.

Abstract: A method of accelerated carrier signal acquisition for a digital communication receiver, the method comprising receiving a carrier signal by a receiver comprising a carrier recovery loop (CRL), setting the CRL to an open loop setting using a processor, setting a numerically controlled oscillator (NCO) within the CRL at a center frequency of the NCO, determining, by the processor, one or more initial parameters of the CRL, calculating an estimate and polarity for a sign frequency detection frequency using a sign frequency detector while simultaneously estimating a Fast Fourier Transform (FFT) frequency by running an FFT using the processor, comparing polarities of the estimates of the sign frequency detection frequency and FFT frequency and determining a frequency offset using the processor, and adjusting one or more parameters of the CRL based on the frequency offset using the processor.

Abstract: A method of rapid non-data aided carrier signal acquisition for a low symbol rate carrier signal, comprising receiving and converting an analog intermediate frequency carrier to a digital carrier signal, down-converting the signal to substantially baseband, reducing a sampling rate of the digital carrier signal using a decimation filter, determining a highest Fast Fourier Transform (FFT) based on a result of one or more FFT's generated by an FFT module using a peak finder, selecting an input source for the FFT module using a multiplexer, generating a frequency estimate of the digital carrier signal using a walking coarse detector, tuning a carrier recovery loop (CRL) based on the frequency estimate generated by the walking coarse detector, determining a final carrier frequency offset estimate using a result of the FFT module, modulation removal, and the peak finder, and programming an oscillator within the CRL to the final carrier frequency offset estimate.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: A method of accelerated carrier signal acquisition for a digital communication receiver, the method comprising receiving a carrier signal by a receiver comprising a carrier recovery loop (CRL), setting the CRL to an open loop setting using a processor. setting a numerically controlled oscillator (NCO) within the CRL at a center frequency of the NCO, determining, by the processor, one or more initial parameters of the CRL, calculating an estimate and polarity for a sign frequency detection frequency using a sign frequency detector while simultaneously estimating a Fast Fourier Transform (FFT) frequency by running an FFT using the processor, comparing polarities of the estimates of the sign frequency detection frequency and FFT frequency and determining a frequency offset using the processor, and adjusting one or more parameters of the CRL based on the frequency offset using the processor.

Abstract: An adaptive equalizer. Implementations of adaptive equalizers may include implementations of 8-QAM adaptive equalizers that may include a signal filter, an adaptive processor coupled to the signal filter and a slicer coupled to the signal filter and the adaptive processor. The slicer may be configured to utilize a plurality of desired signals corresponding to an 8-QAM signal constellation having four quadrants, four levels disposed along the I-axis, and three levels disposed along the Q-axis. The slicer may also be configured to output an error signal by receiving an equalized output signal, processing the equalized output signal by correlating the equalized output signal with a decision region within one of the four quadrants, selecting one of a plurality of desired signals corresponding to the decision region, and calculating the error signal using the desired signal and the equalized output signal.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: An adaptive equalizer. Implementations of adaptive equalizers may include implementations of 8-QAM adaptive equalizers that may include a signal filter, an adaptive processor coupled to the signal filter and a slicer coupled to the signal filter and the adaptive processor. The slicer may be configured to utilize a plurality of desired signals corresponding to an 8-QAM signal constellation having four quadrants, four levels disposed along the I-axis, and three levels disposed along the Q-axis. The slicer may also be configured to output an error signal by receiving an equalized output signal, processing the equalized output signal by correlating the equalized output signal with a decision region within one of the four quadrants, selecting one of a plurality of desired signals corresponding to the decision region, and calculating the error signal using the desired signal and the equalized output signal.