Abstract: A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.

Abstract: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

Abstract: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

Abstract: Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

Abstract: A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.

Abstract: Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.

Abstract: A voltage island system including a hot-switchable voltage bus for IDDQ current measurements. The voltage island system includes a plurality of voltage islands (V1, V2, . . . , Vn), a global power system, and a quiescent power system. The global power system includes a plurality of on-chip global header devices (H1, H2, . . . , Hn) for selectively providing a voltage VDDg to the plurality of voltage islands in response to global header control signals (x1, x2, . . . , xn), respectively. A global VDDg power supply provides power to the global header devices (H1, H2, . . . , Hn) via a VDDg power distribution grid/bus. The quiescent power system includes a plurality of on-chip quiescent header devices (H1q, H2q, . . . , Hnq) for selectively providing a quiescent voltage VDDq to the plurality of voltage islands in response to quiescent header control signals x1q, x2q, . . . , xnq, respectively. A quiescent VDDq power supply provides power to the quiescent header devices via a VDDq power distribution grid/bus.

Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

Abstract: Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

Abstract: Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.

Abstract: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip.

Abstract: A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that each serially extending scan chain comprises a plurality of serially extending segments. A plurality of multiplexors are positioned between the plurality of segments of each scan chain, and are controlled and utilized to connect each segment of the scan chain to the next serial segment in the same scan chain, or to connect each segment of the scan chain to the next serial segment in a lateral adjacent scan chain. Scan in data patterns are introduced into the plurality of serially extending scan chains.

Abstract: A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and one or more corresponding wire segments adjacent to the continuous wire, the continuous wire separated from the one or more corresponding wire segments by a space; and connecting the continuous wire and the one or more wire segments to circuit elements of a defect monitor scan chain, the circuit elements previously inserted into the integrated circuit design.

Abstract: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

Abstract: A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.

Abstract: Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.