Abstract: In one embodiment, a test circuit is coupled to receive a first signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package. In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone. In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.

Abstract: A cache memory system connected between an input/output system having an input/output processor and a computer system having a system bus and a main memory with an input/output portion is provided in which data requested by the input/output processor is retrieved from the input/output portion of the main memory, a memory stores the requested data, and the data in the memory is updated either when the processor is not requesting data or when the processor is requesting data already in the memory. A method for replacing memory pages within a cache memory system is also provided.