Abstract: A system and method for enhancing the utilization of available bandwidth for an uncached device. Data written to the device is done so by striding the available data into multiple data elements of the appropriate size for the uncached device. Data read from the device is retrieved from multiple addresses on the uncached device to avoid unnecessary waits cycles in the processor.

Abstract: An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it.

Abstract: A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

Abstract: An enhanced switch/network adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it.

Abstract: A system and method for enhancing the utilization of available bandwidth for an uncached device. Data written to the device is done so by striding the available data into multiple data elements of the appropriate size for the uncached device. Data read from the device is retrieved from multiple addresses on the uncached device to avoid unnecessary waits cycles in the processor.

Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.

Abstract: The invention provides methods, compositions, and apparatus for performing sensitive detection of analytes, such as biological macromolecules and other analytes, by labeling a probe molecule with an up-converting label. The up-converting label absorbs radiation from an illumination source and emits radiation at one or more higher frequencies, providing enhanced signal-to-noise ratio and the essential elimination of background sample autofluorescence. The methods, compositions, and apparatus are suitable for the sensitive detection of multiple analytes and for various clinical and environmental sampling techniques.

Abstract: A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a “coherency tag” to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques.

Abstract: The invention provides methods, compositions, and apparatus for performing sensitive detection of analytes, such as biological macromolecules and other analytes, by labeling a probe molecule with an up-converting label. The up-converting label absorbs radiation from an illumination source and emits radiation at one or more higher frequencies, providing enhanced signal-to-noise ratio and the essential elimination of background sample autofluorescence. The methods, compositions, and apparatus are suitable for the sensitive detection of multiple analytes and for various clinical and environmental sampling techniques.

Abstract: A power device control system includes a power device having an input gate and first and second output terminals, a controller, and a gate driver for supplying current to the input gate of the power device, comparing a voltage difference between the first and second output terminals, and providing a comparator signal to the controller if the voltage difference is greater than or equal to a predetermined maximum voltage difference. The controller is capable of providing a command signal to the gate driver and pulse width modulating the command signal upon receiving a comparator signal from the gate driver to gradually switch off the power device. The control system can further include a current sensor coupled between one of the first and second output terminals and the controller for supplying a current signal and an integrated current signal to the controller.

Abstract: A power device control system includes a power device having an input gate and first and second output terminals, a controller, and a gate driver for supplying current to the input gate of the power device, comparing a voltage difference between the first and second output terminals, and providing a comparator signal to the controller if the voltage difference is greater than or equal to a predetermined maximum voltage difference. The controller is capable of providing a command signal to the gate driver and pulse width modulating the command signal upon receiving a comparator signal from the gate driver to gradually switch off the power device. The control system can further include a current sensor coupled between one of the first and second output terminals and the controller for supplying a current signal and an integrated current signal to the controller.

Abstract: A duty cycle control circuit, and an associated method, generates an output clock signal having a duty cycle which differs by a desired amount with the duty cycle of an input clock signal. Offset bias signal circuitry generates an offset bias signal which offsets a copy clock signal and an inverted copy clock signal relative to one another by a selected offset bias. The duty cycle of the output clock signal differs with the duty cycle of the input clock signal by an amount which is related to the amplitude of the offset bias signal.

Abstract: A metalization process for the manufacture of hybrid integrated circuit elements including boards and semiconductors to be attached thereto involves applying to a substrate of insulating material such as aluminum oxide, successive layers of sputtered nickel-chromium and nickel, an electroless deposit of nickel-boron and, frequently, an electro-deposited layer of gold. The assembly is then normally heat-treated to stabilize the resistive layer. The addition of the nickel-boron layer provides many advantages in that reliable low-temperature solder connections may be made to it, ultrasonic wire bonds of high reliability may be accomplished with the usual aluminum wire supplied with most discrete components, the heat-treating step is considerably shortened in time with greater stability of resistance values, and the assemblies thus manufactured are capable of operating in comparatively high-temperature environments.

Abstract: A metalization process for the manufacture of hybrid integrated circuit elements including boards and semiconductors to be attached thereto involves applying to a substrate of insulating material such as aluminum oxide, successive layers of sputtered nickel-chromium and nickel, an electroless deposit of nickel-boron and, frequently, an electro-deposited layer of gold. The assembly is then normally heat-treated to stabilize the resistive layer. The addition of the nickel-boron layer provides many advantages in that reliable low-temperature solder connections may be made to it, ultrasonic wire bonds of high reliability may be accomplished with the usual aluminum wire supplied with most discrete components, the heat-treating step is considerably shortened in time with greater stability of resistance values, and the assemblies thus manufactured are capable of operating in comparatively high-temperature environments.