Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

Abstract: The present application provides a memory device.

Abstract: A memory device with modular design and the memory system comprising the same is disclosed. The memory device comprises a substrate plate having a front edge, a rear edge opposite to the front edge, and a top side and a bottom side which are opposite to each other and extend between the front edge and the rear edge; an edge connector positioned at the rear edge and configured to connect to a host connector of a host device; a memory control module positioned on one of the top side and the bottom side of the substrate plate; at least one socket positioned on the top side of the substrate plate and configured to connect to at least one removable memory module; and wherein the memory controller module is electrically coupled to the edge connector and the at least one socket such that the at least one memory module can be accessible by the host device via the memory control module.

Abstract: A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module. Each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) sign

Abstract: A first network device comprises first and second transformers that communicate with a second network device. A switch selectively connects power to the first and second transformers. A physical layer device communicates with the first and second transformers and includes a signal generator, a detector, and a controller that communicates with the switch, the signal generator and the detector. The signal generator generates a test signal comprising n sub-pulses, where n is an integer greater than 2. When the detector detects j pulses that are greater than a predetermined threshold, 1?j<n, the controller supplies power to the second network device, where j is an integer.

Abstract: A first network device supplies power to a second network device in communication therewith. The first network device comprises a physical layer device which includes a pulse generator to generate a test signal comprising n sub-pulses to be transmitted to the second network device, wherein in n being greater than 2. A detector is responsive to the second network device, and a controller is in communication with the detector and the pulse generator. When the detector detects j pulses which are greater than a predetermined threshold, 1?j<n, the controller, responsive to the detector, enables power to be transmitted to the second network device.

Abstract: A high-speed transmission circuit includes an inductive head. The high-speed transmission circuit also includes a non-uniform transmission line having a variable characteristic impedance. The non-uniform transmission line is coupled between the inductive head and an endpoint node such that pulses are conducted over the non-uniform transmission line. The variable characteristic impedance is greater near the inductive head than near the endpoint node.

Abstract: A high speed data transmission channel, preferably embodied in a circuit for writing to a read channel for a hard disk drive, is provided. The channel includes a preamplifier writer, a non-uniform transmission line, and a head. The writer is configured to transmit pulses to the head via the transmission line at a transmission speed. Each pulse has a pulse width. Each pulse may experience interference. The writer is also configured to eliminate interference to each pulse by causing the interference to occur in a differential mode, which causes the interference to cancel out. A transmission time for each pulse is inversely proportional to the transmission speed. The non-uniformity of the transmission line may entail an exponential broadening of a trace width of the transmission line such that when the pulse width is greater than or approximately equal to the transmission time, the pulse propagates from the writer to the head substantially undistorted.