Patents by Inventor Lee-Wei Yen

Lee-Wei Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6468851
    Abstract: A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N+ poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N+ nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N+ poly gate to eliminate a mask level for the dual gate electrodes.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: October 22, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew-Hoe Ang, Eng-Hua Lim, Randall Cher Liang Cha, Jia-Zhen Zheng, Elgin Kiok Boone Quek, Mei-Sheng Zhou, Daniel Lee-Wei Yen
  • Patent number: 5880040
    Abstract: A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: March 9, 1999
    Assignee: Macronix International Co., Ltd.
    Inventors: Shi-Chung Sun, Chun-Hon Chen, Lee-Wei Yen, Chun-Jung Lin
  • Patent number: 5691216
    Abstract: Alignment structures in gaps between patterned features, such as polysilicon wordlines or metal contacts, have a selective effect on various processes to promote self-alignment. The various processes include ion implants for code programming, formation of via cuts, and the polycide process of forming composite layered gates. The alignment structures improve these processes by having a selective effect during etching, deposition, and ion implants. Thus, in one example, to prepare a ROM array for code programming using the ion implantation process, the alignment structures or ion barrier walls are formed between the plurality of wordlines. These ion barrier walls, typically silicon nitride or silicon dioxide, have a height above the substrate that is greater than the height of the wordlines. When viewed from a direction orthogonal to the substrate, only the ion barrier walls and wordlines are visible.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: November 25, 1997
    Assignee: Macronix International Co., Ltd.
    Inventors: Lee-Wei Yen, Wu-An Weng