Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: A twin well forming method for a semiconductor device includes the steps of forming a first insulation layer on a semiconductor substrate, selectively etching the first insulation layer to obtain a first insulation layer pattern and a first buffer insulation, ion-implanting first impurities through the first buffer insulation layer into the semiconductor substrate, forming a second insulation layer on the first insulation layer pattern and the first buffer insulation layer, spreading a planarizing material on the second insulation layer and applying the planarizing material to an annealing treatment to obtain a planarizing material layer, etching back the planarizing material layer and the second insulation layer to expose an upper surface of the first insulation layer pattern, forming a second buffer insulation layer by partially etching the first insulation layer pattern, ion-implanting second impurities through the second buffer insulation layer into the semiconductor substrate, removing the second insulat

Abstract: A fabrication method for a semiconductor memory device with a non-uniformly doped channel(hereinafter, called NUDC) formed in a semiconductor substrate with a thin central portion that becomes gradually thicker toward the edges of the substrate. The method includes forming an impurity-bearing layer on a semiconductor substrate, selectively etching the impurity containing layer in a manner such that the portion of the impurity-bearing layer serving as a gate region is formed to be thin at a central portion thereof and gradually thickens as it nears the edges thereof; forming a first conductive impurity region by driving the impurity from the impurity containing layer into the semiconductor substrate, stripping the impurity containing layer, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive impurity region in the semiconductor substrate at the sides of the gate electrode.