Abstract: Array based memory abstraction in a multiprocessor computing system is disclosed. A plurality of memory resources are operably connected to an interconnect fabric. In a plurality of memory blocks, each memory block represents a contiguous portion of the plurality of memory resources. A cell is operably connected to the interconnect fabric. The cell has an agent with a fabric abstraction block, and the fabric abstraction block includes a block table having an entry for each of the plurality of memory blocks. A memory controller is associated with the agent, is operably connected to the interconnect fabric, and is configured to control a portion of the plurality of memory blocks.

Abstract: In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.

Abstract: Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.

Abstract: An address translation mechanism is provided for use in a partitionable server. In one embodiment, the address translation mechanism provides a sequential zero-based physical memory address space to each of the server's partitions. The translation mechanism maintains mappings between the partitions' physical memory address spaces and a machine memory address space that maps to the real (hardware) memory of the server. The translation mechanism transparently translates physical addresses referenced in memory access requests into machine addresses. As a result, conventional operating systems and other processes that are designed to access sequential zero-based addressed spaces may execute in partitions of a partitionable server without modification. Techniques are also provided for remapping a range of physical memory addresses from one machine (hardware) memory resource to another in a partitionable server, thereby enabling machine memory to be replaced without requiring the server to be rebooted.

Abstract: A memory controller and method for intermittently providing a clock signal to a synchronous memory. While no transactions are occurring, a clock signal is held in an idle state. Upon the start of a transaction with the synchronous memory, the clock signal is activated. When activated, the clock signal functions as a periodic timing reference clock. The clock signal remains active during the transaction. Upon completion of the transaction, the clock signal returns to the idle state. In one embodiment, a finite state machine utilizes a counter to control the process. Upon the start of a transaction with the synchronous memory a new count is loaded in a counter. The value for the new count depends, for example, on the number of commands necessary to complete the transaction. The counter, beginning with the new count, regularly increments. When the counter reaches a maximum value, the clock signal returns to the idle state.

Abstract: Disclosed herein are methods and apparatus which provide a processor with raw, uncorrected data. The uncorrected data (or pre-corrected data) is retrieved from memory and then "bypassed" to a processing unit before its error status is known. Concurrently, error correction hardware determines the data's error status. Since the correct/incorrect indication is the first result available from error correction hardware, this result may be used to gate the actions of a processing unit prior to its taking an irrevocable action with possibly incorrect data. If bypassed data is incorrect, processing unit control logic may flag it as such and read corrected data from the output of error correction hardware. If bypassed data is correct (as will usually be the case), bypassed data may be consumed by a processing unit in due course.

Abstract: In a multiprocessor computer system, wasted bus bandwidth resulting from slow responding slaves is reduced by relinquishing the master that was busied by the slow responding slave, and then causing the slave to effectively arbitrate for bus control on the relinquished master's behalf when the slow responding slave is either available to service the master or has the requested data. In accordance with the disclosed embodiment, the slave effectively arbitrates for bus control on the relinquished master's behalf by placing a unique arbitration code associated with the relinquished master on the bus. The relinquished master detects the presence of its arbitration code and then again arbitrates for bus control so that it may communicate with the slow responding slave.

Abstract: A protocol for carrying out transactions in a multiple-processor computer system comprises: dividing the transaction cycle into four quadrature states, an arbitrate state, an I/O state, a slave address state and a virtual memory state. The protocol enables the processors to determine before arbitrating whether the memory device is busy, which reduces the number of "busied" transactions.