Patents by Inventor Leland Thompson
Leland Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11693806Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.Type: GrantFiled: March 30, 2022Date of Patent: July 4, 2023Assignee: Kioxia CorporationInventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher Delaney, Leland Thompson
-
Publication number: 20220222192Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Inventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher Delaney, Leland Thompson
-
Patent number: 11308015Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.Type: GrantFiled: September 27, 2018Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher Delaney, Leland Thompson
-
Patent number: 10521305Abstract: In one embodiment, a solid state drive (SSD) with power loss protection (PLP) includes a SSD controller, a secondary controller and a power circuit configured to supply power to the SSD from a power source during normal operation and backup power from a backup power source in response to a loss of power supplied by the power source. In the event of a loss of power, the secondary controller is configured to track the holdup time, or duration of time for which the primary controller can operate on backup power. In one embodiment, the holdup time tracked by the secondary controller is stored in a non-volatile memory in communication with the secondary controller.Type: GrantFiled: April 29, 2016Date of Patent: December 31, 2019Assignee: Toshiba Memory CorporationInventors: Christopher Delaney, Leland Thompson, John Hamilton, Gordon Waidhofer, Ali Aiouaz
-
Publication number: 20190243578Abstract: In one embodiment, an implementation of a solid state drive (SSD) enables efficient use of volatile memory capacity by receiving data from a host interface communicatively coupled to an SSD, storing the data in one of a plurality of units comprising free memory within a volatile memory within the SSD, writing the data stored in the unit of the volatile memory to a memory buffer within a non-volatile memory within the SSD, and identifying the unit of the volatile memory as free memory after writing the data stored in the unit of the volatile memory to the memory buffer within the non-volatile memory. In one embodiment, the data is protected using a reliability mechanism. In another embodiment, a parity value associated with the data is calculated while transferring the data from the unit of the volatile memory to the memory buffer.Type: ApplicationFiled: February 8, 2018Publication date: August 8, 2019Inventors: Leland Thompson, Gordon Waidhofer, Neil Buxton
-
Publication number: 20190026244Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.Type: ApplicationFiled: September 27, 2018Publication date: January 24, 2019Inventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher Delaney, Leland Thompson
-
Patent number: 10120823Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.Type: GrantFiled: September 25, 2015Date of Patent: November 6, 2018Assignee: Toshiba Memory CorporationInventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher Delaney, Leland Thompson
-
Publication number: 20180260319Abstract: A solid state drive (SSD) and a method for writing user data and system data is disclosed. In one embodiment, the SSD includes a memory controller, a host interface communicatively coupled to the memory controller, and one or more NAND flash memory devices communicatively coupled to the memory controller. The memory controller is configured to write both a user data received via the host interface and a system data generated by the memory controller to one or more blocks of the NAND flash memory devices such that the one or more blocks contain both user data and system data. In one embodiment, the memory controller is figured to divide the system data into one or more segments having a uniform size, and append a header to each segment of system data before writing the system data to the one or more blocks of the NAND flash memory devices.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Inventors: Leland Thompson, Chris Delaney, Gordon Waidhofer
-
Patent number: 9910619Abstract: A solid state drive includes a dual buffer for buffering incoming write data prior to committal to a non-volatile memory. The buffer is operated to provide a temporary backup of dirty data pending successful completion of a host transfer. The dual buffer may be operated as a primary buffer and a secondary buffer. The primary buffer may be used as the default buffer during normal operation. The secondary buffer is written to during a host transfer that is a cache write to dirty data. A copying process may be used to copy data between the primary and the secondary buffer to preserve the backup data pending successful completion of the host transfer.Type: GrantFiled: December 21, 2015Date of Patent: March 6, 2018Assignee: Toshiba Memory CorporationInventors: Christopher Delaney, Gordon Waidhofer, Leland Thompson, Ali Aiouaz
-
Patent number: 9910767Abstract: On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.Type: GrantFiled: December 15, 2014Date of Patent: March 6, 2018Assignee: Toshiba Memory CorporationInventors: Gordon Waidhofer, Christopher Delaney, Leland Thompson
-
Publication number: 20170315889Abstract: In one embodiment, a solid state drive (SSD) with power loss protection (PLP) includes a SSD controller, a secondary controller and a power circuit configured to supply power to the SSD from a power source during normal operation and backup power from a backup power source in response to a loss of power supplied by the power source. In the event of a loss of power, the secondary controller is configured to track the holdup time, or duration of time for which the primary controller can operate on backup power. In one embodiment, the holdup time tracked by the secondary controller is stored in a non-volatile memory in communication with the secondary controller.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Christopher Delaney, Leland Thompson, John Hamilton, Gordon Waidhofer, Ali Aiouaz
-
Publication number: 20170177276Abstract: A solid state drive includes a dual buffer for buffering incoming write data prior to committal to a non-volatile memory. The buffer is operated to provide a temporary backup of dirty data pending successful completion of a host transfer. The dual buffer may be operated as a primary buffer and a secondary buffer. The primary buffer may be used as the default buffer during normal operation. The secondary buffer is written to during a host transfer that is a cache write to dirty data. A copying process may be used to copy data between the primary and the secondary buffer to preserve the backup data pending successful completion of the host transfer.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Inventors: Christopher Delaney, Gordon Waidhofer, Leland Thompson, Ali Aiouaz
-
Publication number: 20170177233Abstract: A solid state drive includes a dual buffer for buffering incoming write data prior to committal to a non-volatile memory. The buffer is operated to provide a temporary backup of dirty data pending successful completion of a host transfer. The dual buffer may be operated as a primary buffer and a secondary buffer. The primary buffer may be used as the default buffer during normal operation. The secondary buffer is written to during a host transfer that is a cache write to dirty data. A copying process may be used to copy data between the primary and the secondary buffer to preserve the backup data pending successful completion of the host transfer.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Inventors: Christopher Delaney, Gordon Waidhofer, Leland Thompson, Ali Aiouaz
-
Publication number: 20160172014Abstract: On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.Type: ApplicationFiled: December 15, 2014Publication date: June 16, 2016Inventors: Gordon WAIDHOFER, Christopher DELANEY, Leland THOMPSON
-
Publication number: 20070236331Abstract: An RFID tag can have a state diagram with a timed state that automatically expires after a timeout time. RFID reader systems, software, tags, circuits and methods are provided that send an interim command to cancel the impending automatic expiration.Type: ApplicationFiled: August 11, 2006Publication date: October 11, 2007Applicant: Impinj, Inc.Inventors: Leland Thompson, Omar Khwaja, Ali Aiouaz, Christopher J. Diorio