Patents by Inventor Len Mei
Len Mei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8125020Abstract: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.Type: GrantFiled: October 15, 2007Date of Patent: February 28, 2012Assignee: Promos Technologies Pte. LtdInventors: Yue-Song He, Len Mei
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Publication number: 20100323511Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.Type: ApplicationFiled: August 31, 2010Publication date: December 23, 2010Inventors: Yue-Song He, Len Mei
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Patent number: 7816726Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.Type: GrantFiled: December 20, 2007Date of Patent: October 19, 2010Assignee: ProMOS Technologies Pte. Ltd.Inventors: Yue-Song He, Len Mei
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Patent number: 7808032Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer.Type: GrantFiled: June 25, 2008Date of Patent: October 5, 2010Assignee: ProMOS Technologies Pte. Ltd.Inventors: Yue-Song He, Len Mei
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Publication number: 20090321806Abstract: Substrate isolation regions (570) initially protrude upward above a semiconductor substrate (520) but are later etched down. Before they are etched down, floating gate layer (590) is deposited and etched or polished off the top surfaces of the substrate isolation regions. The floating gate layer thus has upward protrusions overlying sidewalls of the substrate isolation regions. When the substrate isolation regions are etched down, the floating gate layer's upward protrusions' outer sidewalls become exposed. The upward protrusions serve to increase the capacitance between the floating and control gates. The floating gates' bottom surfaces are restricted to the active areas (564) not to overlie the substrate isolation regions. Other features are also provided.Type: ApplicationFiled: June 26, 2008Publication date: December 31, 2009Inventors: Len Mei, Yue-Song He
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Publication number: 20090256221Abstract: A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a plurality of lines of the material on the surface of the substrate, and etching the lines of the target material so as to form a rectangular matrix of substantially similar, very small isolated dots of the target material on the substrate. By the successive formation of orthogonally intersecting linear patterns on the substrate, including the formation and use of “hard” etch masks, spacer approach and selective etching techniques, the method enables very small (<65 nm) isolated dots of the target material to be formed on the substrate reliably and with the use of conventional 193 nm wavelength photolithographic methods and apparatus.Type: ApplicationFiled: April 11, 2008Publication date: October 15, 2009Inventors: Len Mei, Yue-Song He
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Publication number: 20090251972Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.Type: ApplicationFiled: April 3, 2008Publication date: October 8, 2009Inventors: Yue-Song He, Len Mei
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Publication number: 20090184359Abstract: A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Inventors: Yue-Song He, Len Mei
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Publication number: 20090159957Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Inventors: Yue-Song He, Len Mei
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Publication number: 20090101961Abstract: The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.Type: ApplicationFiled: October 22, 2007Publication date: April 23, 2009Inventors: Yue-Song He, Len Mei
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Publication number: 20090096013Abstract: A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias is to the control gates directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Inventors: Yue-Song He, Len Mei
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Publication number: 20090085069Abstract: In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant region defines shallow source/drain regions for floating gate transistors of the memory cells. The size of the metal silicide insets are controlled to not compromise isolation PN junctions defined by the shallow and deep implant region. In one embodiment, the metal silicide insets include nickel.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Inventors: Len MEI, Yue-Song HE
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Patent number: 7452776Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer.Type: GrantFiled: April 24, 2007Date of Patent: November 18, 2008Assignee: ProMOS Technoloies Pte. Ltd.Inventors: Yue-Song He, Len Mei
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Publication number: 20080265305Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer.Type: ApplicationFiled: June 25, 2008Publication date: October 30, 2008Inventors: Yue-Song He, Len Mei
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Publication number: 20080266949Abstract: A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer.Type: ApplicationFiled: April 24, 2007Publication date: October 30, 2008Inventors: Yue-Song He, Len Mei
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Publication number: 20050205411Abstract: A physical vapor deposition apparatus is provided. The physical vapor deposition apparatus comprises: a reaction chamber; and an electromagnet magnetron device disposed above and outside said reaction chamber, wherein when performing a physical vapor deposition process, the magnetic poles of said electromagnet magnetron device are reversed in-situ to reduce the possibility of asymmetric deposition of the thin film on the sidewalls of the opening.Type: ApplicationFiled: July 29, 2004Publication date: September 22, 2005Inventors: Tai-Yuan Chen, Len Mei
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Patent number: 6495411Abstract: A method for fabricating deep-submicron DRAMs containing a deep trench capacitor with enlarged sidewall surface for improved storage capacitance. It includes the main steps of: (a) forming a silicon substrate having a (110) crystalline plane and a (111) crystalline plane; (b) forming a vertically extending deep trench into a crystalline silicon substrate; (c) filling the deep trench with a first dielectric material to form a first dielectric filler layer; (d) etching back the first dielectric filler layer to a first depth; (e) forming a dielectric collar from a second dielectric material which hangs on the sidewall of the deep trench extending from the opening of the trench to the first depth; (f) removing the first dielectric filler layer with a selective etching process; and (g) under a carefully timed exposure, using an isotropic etching solution which has high etching rate in the (110) plane and low etching rate in the (111) plane to form a roughened surface on the bottom surface of the deep trench.Type: GrantFiled: October 10, 2000Date of Patent: December 17, 2002Assignees: ProMos Technology Inc., Mosel Vitelic Inc., Siemens AGInventor: Len Mei
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Patent number: 6232171Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more.Type: GrantFiled: June 8, 1999Date of Patent: May 15, 2001Assignees: ProMOS Technology, Inc., Mosel Vitelic Inc., Siemens AGInventor: Len Mei
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Patent number: 6007405Abstract: A chemical mechanical polisher for polishing a surface of a semiconductor wafer is disclosed. The polisher comprises: a polishing table for holding a polishing pad; a rotatable wafer chuck for holding said semiconductor wafer against said polishing pad; an electrical lapping guide secured to said wafer chuck, said electrical lapping guide comprising: a polishable resistive sensor that has a variable resistance dependent upon the amount of material removed from said resistive sensor during polishing; and a bias means for applying a bias to said resistive sensor such that said resistive sensor is in contact with said polishing pad during polishing; a resistance sensing means for determining said variable resistance of said resistive sensor; and a microprocessor for determining the amount of material polished from said resistive sensor based upon said variable resistance.Type: GrantFiled: July 17, 1998Date of Patent: December 28, 1999Assignee: ProMOS Technologies, Inc.Inventor: Len Mei