Abstract: A battery operated computer includes a battery having a plurality of serially connected banks of battery cells that are monitored during operation of the computer to detect a nearly depleted battery bank and a fully depleted battery bank. The computer also includes a plurality of microprocessors including a host or system processor, a service processor and a power subsystem processor. When a nearly depleted battery bank is detected, the power subsystem processor is interrupted and it sends a message to the service processor which in turn interrupts the host processor. An interrupt handler then powers down the system. When a fully depleted battery bank is detected, the battery is immediately disconnected and the system is shutoff to prevent polarity or cell reversal.

Abstract: A digitizer tablet computer has a host processor connected to a service processor which, in turn, is connected to a digitizer controller and to a power subsystem microcontroller. A battery supplies the primary power for operating the computer but the computer is also connectable to an external source of DC power to charge the battery and to operate the computer when it is not running on battery power. The service processor includes a battery gauge the contents of which indicate how much power is left in the battery and how much time remains at the current rate of power consumption before the power runs out. The amount of remaining power in the gauge is determined by keeping track of power consumed, power added, and power lost during off periods. The use of the second derivative of a voltage versus time discharge curve creates a point from which relative accurate estimates can be made of how much longer the computer can be operated.

Abstract: An FET substrate voltage generator circuit is disclosed for converting a single power supply and ground potential to a negative potential having an absolute value whose magnitude is greater than the power supply potential and applying that potential to the substrate of an integrated circuit upon which it is formed. The circuit dissipates less power per unit of current supplied by the circuit and occupies less space than do prior art circuits. The circuit applies the principle of voltage doubling to a first capacitor to achieve the desired voltage magnitude across a second capacitor and then applies the principle of a.c. coupling to that second capacitor connected through an impedance to the first capacitor, to achieve the desired polarity inversion for the substrate voltage to be generated. This circuit provides the current generating capacity necessary to drive the substrate to a negative voltage and sink the required current so as to maintain the substrate at an adequate negative bias.

Abstract: The problem of a race condition in the precharged drain type FET read only storage circuits is avoided in the invention disclosed herein, by applying the bit decode signal to the source of the array device, so that the drain cannot be discharged through the FET array device unless both the bit line connected to the source and word line connected to the gate have on-signals. Thus, the memory circuit can be operated in a faster cycle because the word and bit signals may be made coincident.