Patents by Inventor Leon J. Sigal
Leon J. Sigal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9990454Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.Type: GrantFiled: June 3, 2016Date of Patent: June 5, 2018Assignee: International Business Machines CorporationInventors: Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets, Michael R. Scheuermann, Leon J. Sigal, Richard A. Wachnick, James D. Warnock
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Publication number: 20170351785Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventors: Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets, Michael R. Scheuermann, Leon J. Sigal, Richard A. Wachnick, James D. Warnock
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Patent number: 9552455Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.Type: GrantFiled: February 3, 2015Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, Leon J. Sigal, James D. Warnock
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Publication number: 20160224717Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.Type: ApplicationFiled: February 3, 2015Publication date: August 4, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, Leon J. Sigal, James D. Warnock
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Patent number: 9104832Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.Type: GrantFiled: January 22, 2014Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: John E. Barwin, III, Jason Chung, Amol A. Joshi, William J. Livingstone, Leon J. Sigal, Brian Worth, Paul S. Zuchowski
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Publication number: 20150205906Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: International Buiness Machines CorporationInventors: John E. Barwin, III, Jason Chung, Amol A. Joshi, William J. Livingstone, Leon J. Sigal, Brian Worth, Paul S. Zuchowski
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Patent number: 8914765Abstract: A method of generating a power grid to supply current to a plurality of cells of an integrated circuit includes routing an initial power grid representing a power usage estimate for the plurality of cells. The method also includes performing power grid analysis prior to routing of signal wires to make a determination of whether the initial power grid meets power requirements of the integrated circuit, and selectively modifying portions of the initial power grid based on the performing the power grid analysis to generate the power grid.Type: GrantFiled: January 15, 2013Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Leon J. Sigal, James D. Warnock
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Publication number: 20140201695Abstract: A method of generating a power grid to supply current to a plurality of cells of an integrated circuit includes routing an initial power grid representing a power usage estimate for the plurality of cells. The method also includes performing power grid analysis prior to routing of signal wires to make a determination of whether the initial power grid meets power requirements of the integrated circuit, and selectively modifying portions of the initial power grid based on the performing the power grid analysis to generate the power grid.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leon J. Sigal, James D. Warnock
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Patent number: 8354858Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: GrantFiled: January 8, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Publication number: 20110102042Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: January 8, 2011Publication date: May 5, 2011Applicant: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7888959Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: GrantFiled: September 19, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7589565Abstract: An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local clock buffer circuit having a plurality of outputs. The local clock buffer circuit is connected to the global clock circuit. The local clock buffer circuit is capable of producing a secondary timing signal based on the primary timing signal. The circuit also includes a latch connected to the local clock buffer circuit. The latch is capable of producing a select signal that controls which outputs of the plurality of outputs are active. Only a third signal, based on the secondary timing signal, controls an operation of the latch.Type: GrantFiled: February 1, 2008Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: Leon J. Sigal, James D. Warnock, Dieter F. Wendel
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Publication number: 20090199038Abstract: An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local clock buffer circuit having a plurality of outputs. The local clock buffer circuit is connected to the global clock circuit. The local clock buffer circuit is capable of producing a secondary timing signal based on the primary timing signal. The circuit also includes a latch connected to the local clock buffer circuit. The latch is capable of producing a select signal that controls which outputs of the plurality of outputs are active. Only a third signal, based on the secondary timing signal, controls an operation of the latch.Type: ApplicationFiled: February 1, 2008Publication date: August 6, 2009Inventors: Leon J. Sigal, James D. Warnock, Dieter F. Wendel
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Patent number: 7568173Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.Type: GrantFiled: June 14, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Leon J. Sigal, Robert F. Walker, Pieter J. Woeltgens, Xiaoyun K. Wu, Xin Yuan
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Publication number: 20090134925Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: September 19, 2007Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Publication number: 20080313581Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.Type: ApplicationFiled: June 14, 2007Publication date: December 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Leon J. Sigal, Robert F. Walker, Pieter J. Woeltgens, Xiaoyun K. Wu, Xin Yuan
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Patent number: 7456671Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.Type: GrantFiled: January 11, 2007Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Phillip J. Restle, Leon J. Sigal
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Publication number: 20080169857Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlie C Hwang, Phillip J. Restle, Leon J. Sigal
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Patent number: 7100144Abstract: A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.Type: GrantFiled: December 9, 2003Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Hans M. Jacobson, Prabhakar N. Kudva, Leon J. Sigal
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Patent number: 6629298Abstract: A method (and a system for using the method) for automating a slew rate analysis between two or more circuits on a semiconductor chip. The method includes the steps of: receiving as input one or more input parameters characterizing the physical medium through which the signal propagation occurs (the net) and the electrical characteristics of signals transmitted between the circuits; and providing as output one or more output parameters characterizing the appropriate solution for physical implementation of the circuit(s) and net(s) which satisfy the performance requirements of the system. The receiving step can comprise any one of: providing a hierarchical signal name cross-reference defining a name for the signal for a given hierarchy level of the circuits; providing a set of one or more boolean equations used to generate the one or more output parameters from the one or more input parameters; providing a physical design information for the circuits; and providing a timing information for the signals.Type: GrantFiled: November 10, 1999Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Peter J. Camporese, Adam R. Jatkowski, Leon J. Sigal, Patrick M. Williams