Abstract: The present invention provides methods, systems, devices, and computer program instructions for enabling low-power wireless devices (such as wireless telephones and personal digital assistants, or PDAs) to connect to a fast wired or wireless voice/data network. A novel relay point device, referred to as an “extension point”, is defined that flexibly extends the effective reach of network access points. Use of extension points enables the network infrastructure to be expanded (and subsequently re-configured, if necessary) simply and cost-effectively, requiring little or no additional physical wiring. The defined techniques provide an infrastructure that is scalable, supporting a large number of end users without substantial degradation to connection establishment time and data rates. Using the disclosed techniques, end devices are able to reach network services, and to communicate with other end devices, beyond the nominal working range of these devices and without limitation to the numbers of such devices.

Abstract: The present invention provides methods, systems, devices, and computer program instructions for enabling low-power wireless devices (such as wireless telephones and personal digital assistants, or PDAs) to connect to a fast wired or wireless voice/data network. A novel relay point device, referred to as an “extension point”, is defined that flexibly extends the effective reach of network access points. Use of extension points enables the network infrastructure to be expanded (and subsequently re-configured, if necessary) simply and cost-effectively, requiring little or no additional physical wiring. The defined techniques provide an infrastructure that is scalable, supporting a large number of end users without substantial degradation to connection establishment time and data rates.

Abstract: A singlecast interactive radio system of the invention delivers digitized audio-based content to subscribers, upon their request, economically and with human voice quality. The system includes personal radio station servers, and a plurality of user terminals, and exploits one of the existing wireless communication networks as a transmission medium. A highly compressed voice-based information content is stored on data network servers, such as Internet World Wide Web servers. The personal radio station server stores multiple subscriber's profiles with topics of individual interest, assembles a content material from various Web sites according to the topics, and transmits the content to a subscriber's user terminal on subscriber's request over the wireless digital network.

Abstract: A gateway enables point to multipoint connectivity from voice, data, or SVD clients over voice and data networks. The gateway connects one or more known voice networks (e.g. telephone networks) and one or more data networks (e.g. LANs, WANs, and internet) so that clients on either network may access any of the networks via various devices like analog telephones, data modems, SVD modems, or direct data network connections (e.g., ethernet, token ring). The gateway has connections to both the data network(s) as well as the voice network(s). The gateway is capable of splitting a signal with both voice and data streams and routing either and/or both of these streams over the voice network alone, the data network, or both. A process, executing on the gateway enables the gateway to establish connections on gateway paths and to control and direct a flow of voice and data information between the destinations on these networks.

Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer.

Abstract: An information signal content authoring system is provided. The authoring system includes a speech analyzer, responsive to a spoken utterance signal provided by a narrator. The spoken utterance signal is representative of information available to the narrator. The speech analyzer generates a speech signal representative of one or more prosodic parameters associated with the narrator. A text-to-speech converter, responsive to a text signal representative of the information available to the narrator, generates a phonetic representation signal from the text signal and synthesizes a speech signal from the text signal. The text-to-speech converter also generates one or more prosodic parameters from the text signal.

Abstract: An image buffer is described for an X.times.Y pixel display, which image buffer stores compressed image pixel data for a plurality of n.times.m matrices of pixels, each matrix represented by a pair of color codes and MASK having nm bit position, each positions mapping to a pixel in the matrix, a manifested bit value in a MASK bit position defining the color code assigned to a mapped pixel. The image buffer includes serial registers for feeding pixel color code values to a buffer serial output and multiplexers for providing n bit values from the MASK on n of its output lines. Gating circuitry, controlled by bit values on the output lines, are operative to gate either a first set of inputs or a second set of inputs into the shift registers. Control circuitry is provided for feeding a pair of color codes and the MASK bit values to the gating circuits and multiplexers, respectively, and for serially operating the serial shift registers in response to the gating of the inputs from the gating circuits.

Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules. The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.

Abstract: SIMD computer architecture is used in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M.times.N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M.times.

Abstract: Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers.

Abstract: A high-speed communications network (10) provides singlecast, multicast, or broadcast image data capability and is implemented utilizing the High-Performance Parallel Interface (HPPI) as a physical channel. A server (12) includes both a HPPI receiver and transmitter. Workstations (18) support a HPPI-compatible receiver (14b), but require only a simplified HPPI output port (20). The workstations are connected such the receiver port of each is driven by data and control signals from an upstream server HPPI transmitter port. Handshaking signals, generated by the receiver ports, ripple upstream to the server or to an upstream workstation output port. A packet of data bursts corresponds to either a complete image frame, or to a rectangular subsection thereof, referred to as a window. A first burst is defined to be a Header burst and contains an Image Header that specifies addresses of addressed workstations. Following the Header burst are image data bursts containing pixel data organized in raster format.

Abstract: Image conversion method and apparatus that provides for (a) storing in a first memory a first image field; (b) storing in a second memory a second image field; (c) reading the first and the second memories; (d) simultaneously displaying on a display screen the first and the second image fields as a single image frame; and (e) while performing the step of reading the method includes a step of storing in a third memory a third image field. The first, second and third memories are provided as a frame buffer having a 3.times.3 memory block organization. For image fields numbered 1, 2, 3, 4, 5 . . . n . . . the system of the invention reads the image fields two at a time in accordance with a predetermined sequence given by: 1 and 2, 2 and 3, 3 and 4, 4 and 5, (n-1) and n, n and (n+1). A high resolution frame length is selected to be longer than or shorter than a television field period.

Abstract: A circuit for interfacing between a digital-television circuit for producing pixel data for television images and a computer graphics display permits rapid scaling and positioning of live television images on the graphics display. In a preferred embodiment, the digital-television/computer-graphics interface circuit of the invention includes memory for storing a horizontal-scaling bit pattern and a vertical-scaling bit pattern. Such a preferred interface circuit is adapted to receive digital-television pixel data from the digital television circuit and, on a pixel-by-pixel basis depending on the state of corresponding bits in the horizontal-scaling bit pattern, to skip the pixel in the case of image contraction and to replicate the pixel in the case of image expansion.

Abstract: An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.

Abstract: A locking mechanism is incorporated in a high-resolution video display system including a monitor, a computer for providing controls signals to said display system and two frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer.

Abstract: An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values.

Abstract: A stereoscopic sursor for high-resolution stereoscopic raster display is addressable to any arbitrary point on the display and simulates depth by alternately displaying left and right patterns that are offset from one another in a horizontal (x-axis) direction. Left and right views of the cursor are alternately displayed at the display frame rate, while a shutter mechanism presents the appropriate views to the viewer's eyes. To further enhance the perception of depth, monoscopic depth cues are provided by varying the cursor's color, size, transparency and/or pattern as the cursor moves in depth.

Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor.

Abstract: A method and apparatus for synchronizing two independent rasters, such that a standard TV video and a high resolution computer generated graphics video may each be displayed on a high resolution graphics monitor. This is accomplished utilizing dual frame buffers. A TV frame buffer, comprises a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resolution graphics monitor. A high resolution frame buffer in a computer is utilized to store high resolution graphics which is read out synchronously with the high resolution graphics monitor. A switching mechanism selects which of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion.

Abstract: An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of digital data (COMVIDOUT) comprising separate luminance and chrominance fields, from a digital TV source associated with each display node which data represents a scaled video window, (2) the local system clock (SCLK), (3) vertical and horizontal communication sync signals (COMVSOUT and COMSHOUT), (4) luminance and chrominance clock enable signals (COMYOCE and COMCOCE) based on a scaling algorithm utilized in the transmitting video device to insure that both the proper pixels and the proper luminance and chrominance fields associated with these pixels are selected by the communications device for transmission.