Abstract: A plurality of synchronized phase generators are provided in a mainframe computer of the type having unit card each of which contain a plurality of very large scale integrated (VLSI) logic chips. Each logic chip has its own on-chip phase generator which is controlled by off-chip control signals. The on-chip phase generations each comprise output phase control gates coupled to: an on-chip start shift register, a stop shift register, clock shift registers which provide the phase of the clock, and start-stop run controls all of which are coupled to off-chip control signals and to the output phase control gates which are synchronized to eliminate distortion and skew between phase generators on different logic chips.