Patents by Inventor Leonard Franklin Register, II
Leonard Franklin Register, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180323370Abstract: A magnetic solid state device is disclosed. The magnetic solid state device includes a substrate and a topological insulator deposited on top of the substrate. The magnetic solid state device also includes a first perpendicular magnetic anisotropy (PMA) bit having a reference PMA layer located on the topological insulator, and a second PMA bit having a free PMA layer located on the topological insulator. A gate contact is utilized to receive various predetermined voltages for controlling the Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions between the reference PMA layer in the first PMA bit and the free PMA layer in the second PMA bit.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventors: LEONARD FRANKLIN REGISTER, II, BAHNIMAN GHOSH, RIK DEY, SANJAY KUMAR BANERJEE
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Patent number: 10121962Abstract: A magnetic solid state device is disclosed. The magnetic solid state device includes a substrate and a topological insulator deposited on top of the substrate. The magnetic solid state device also includes a first perpendicular magnetic anisotropy (PMA) bit having a reference PMA layer located on the topological insulator, and a second PMA bit having a free PMA layer located on the topological insulator. A gate contact is utilized to receive various predetermined voltages for controlling the Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions between the reference PMA layer in the first PMA bit and the free PMA layer in the second PMA bit.Type: GrantFiled: May 8, 2017Date of Patent: November 6, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Leonard Franklin Register, II, Bahniman Ghosh, Rik Dey, Sanjay Kumar Banerjee
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Patent number: 9825218Abstract: A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits.Type: GrantFiled: October 13, 2015Date of Patent: November 21, 2017Assignee: Board of Regents, The University of Texas SystemInventors: Allan MacDonald, Leonard Franklin Register, II, Emanuel Tutuc, Inti Sodemann, Hua Chen, Xuehao Mou, Sanjay K. Banerjee
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Publication number: 20170104151Abstract: A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits.Type: ApplicationFiled: October 13, 2015Publication date: April 13, 2017Inventors: Sanjay K. Banerjee, Allan MacDonald, Leonard Franklin Register, II, Emanuel Tutuc, Inti Sodemann, Hua Chen, Xuehao Mou
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Patent number: 8629427Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.Type: GrantFiled: April 29, 2011Date of Patent: January 14, 2014Assignee: Texas A&M UniversityInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Bhagawan R. Sahu, Priyamvada Jadaun, Jiwon Chang
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Publication number: 20120273763Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Bhagawan R. Sahu, Priyamvada Jadaun, Jiwon Chang
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Patent number: 8263967Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.Type: GrantFiled: May 1, 2012Date of Patent: September 11, 2012Assignee: Board of Regents, The University of Texas SystemsInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
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Publication number: 20120212257Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.Type: ApplicationFiled: May 1, 2012Publication date: August 23, 2012Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
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Patent number: 8188460Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.Type: GrantFiled: November 24, 2009Date of Patent: May 29, 2012Assignee: Board of Regents, The University of Texas SystemInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
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Patent number: 8008649Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.Type: GrantFiled: February 13, 2009Date of Patent: August 30, 2011Assignee: Board of Regents, The University of Texas SystemInventors: Leonard Franklin Register, II, Sanjay Banerjee
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Publication number: 20100207101Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Board of Regents, The University of Texas SystemInventors: Leonard Franklin Register, II, Sanjay Banerjee
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Publication number: 20100127243Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.Type: ApplicationFiled: November 24, 2009Publication date: May 27, 2010Applicant: The Board of Regents The University of Texas SystemInventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emmanuel Tutuc