Patents by Inventor LEONARD GULER
LEONARD GULER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145598Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Bruce E. BEATTIE, Leonard GULER, Biswajeet GUHA, Jun Sung KANG, William HSU
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Patent number: 11929396Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.Type: GrantFiled: April 20, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
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Patent number: 11901458Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.Type: GrantFiled: June 27, 2022Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Bruce E. Beattie, Leonard Guler, Biswajeet Guha, Jun Sung Kang, William Hsu
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Publication number: 20230320057Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Clifford Ong, Leonard Guler, Mohit Haran, Smita Shridharan, Reken Patel, Charles Wallace, Chanaka Munasinghe, Pratik Patel
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Publication number: 20230209798Abstract: Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Clifford Ong, Leonard Guler, Mohammad Hasan, Tahir Ghani
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Publication number: 20230209797Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Clifford Ong, Leonard Guler, Smita Shridharan, Zheng Guo, Eric Karl, Tahir Ghani
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Publication number: 20230209799Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Clifford Ong, Dan Lavric, Leonard Guler, YenTing Chiu, Smita Shridharan, Zheng Guo, Eric A. Karl, Tahir Ghani
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Publication number: 20230114214Abstract: Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.Type: ApplicationFiled: September 24, 2021Publication date: April 13, 2023Applicant: Intel CorporationInventors: Stephen Cea, Biswajeet Guha, Leonard Guler, Tahir Ghani, Sean Ma
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Publication number: 20230089815Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: Leonard GULER, Nick LINDERT, Biswajeet GUHA, Swaminathan SIVAKUMAR, Tahir GHANI
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Patent number: 11569231Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.Type: GrantFiled: March 15, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Stephen D Snyder, Leonard Guler, Richard Schenker, Michael K Harper, Sam Sivakumar, Urusa Alaan, Stephanie A Bojarski, Achala Bhuwalka
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Publication number: 20220413376Abstract: Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Leonard Guler, Tahir Ghani, Charles Wallace, Hossam Abdallah, Dario Farias, Tsuan-Chung Chang, Chia-Ho Tsai, Chetana Singh, Desalegne Teweldebrhan, Robert Joachim, Shengsi Liu
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Patent number: 11538937Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.Type: GrantFiled: January 4, 2019Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Leonard Guler, Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar, Tahir Ghani
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Publication number: 20220336668Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.Type: ApplicationFiled: June 27, 2022Publication date: October 20, 2022Inventors: Bruce E. BEATTIE, Leonard GULER, Biswajeet GUHA, Jun Sung KANG, William HSU
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Publication number: 20220246721Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: INTEL CORPORATIONInventors: William HSU, Biswajeet GUHA, Leonard GULER, Souvik CHAKRABARTY, Jun Sung KANG, Bruce BEATTIE, Tahir GHANI
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Patent number: 11404578Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-?”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.Type: GrantFiled: June 22, 2018Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Bruce E. Beattie, Leonard Guler, Biswajeet Guha, Jun Sung Kang, William Hsu
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Publication number: 20220173034Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Applicant: Intel CorporationInventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius
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Patent number: 11342411Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.Type: GrantFiled: June 29, 2018Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
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Patent number: 11251117Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.Type: GrantFiled: September 5, 2019Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius
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Patent number: 11189614Abstract: A grating structure has a plurality of grating members that extend upward from a base in a spaced-apart parallel relationship and include an end member. For example, the grating structure is a plurality of semiconductor fins on a base. The base can be any structure underlying the grating members. The grating members have a member width and a member height. Adjacent grating members are spaced by a grating spacing. A process artifact is adjacent the end member and is spaced from the end member by a horizontal distance consistent with the member spacing. In some cases, the process artifact can be a stub of a second material on or otherwise extending from the base adjacent an end member of the grating structure. In other cases, the process artifact can be a recess in or otherwise extending into the base adjacent an end member of the grating structure.Type: GrantFiled: March 16, 2018Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Leonard Guler, Elliot Tan
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Publication number: 20210074632Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Applicant: Intel CorporationInventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius