Patents by Inventor Leonard J. Gardecki
Leonard J. Gardecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7670437Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.Type: GrantFiled: May 8, 2008Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Duane E. Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard J. Gardecki, William L. Hammond, Kibby B. Horsford, Charles R. Ramsey
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Publication number: 20080202421Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.Type: ApplicationFiled: May 8, 2008Publication date: August 28, 2008Inventors: Duane E. Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard J. Gardecki, William L. Hammond, Kibby B. Horsford, Charles R. Ramsey
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Patent number: 7410919Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.Type: GrantFiled: June 27, 2003Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Duane E Allen, Brian K Burnor, Thomas A Dotolo, Leonard J Gardecki, William L Hammond, Kibby B Horsford, Charles R Ramsey
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Patent number: 7288492Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.Type: GrantFiled: July 19, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Leonard J. Gardecki, James R. Palmer, Erik M. Probstfield, Adolf E. Wirsing
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Patent number: 7138326Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.Type: GrantFiled: July 23, 2003Date of Patent: November 21, 2006Assignee: International Business Machines Corp.Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
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Patent number: 6951775Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.Type: GrantFiled: June 28, 2003Date of Patent: October 4, 2005Assignee: International Business Machines CorporationInventors: Leonard J. Gardecki, James R. Palmer, Erik M. Probstfield, Adolf E. Wirsing
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Publication number: 20040266159Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.Type: ApplicationFiled: June 28, 2003Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Leonard J Gardecki, James R Palmer, Erik M Probstfield, Adolf E Wirsing
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Publication number: 20040261977Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Applicant: International Business Machines CorporationInventors: Duane E. Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard J. Gardecki, William L. Hammond, Kibby B. Horsford, Charles R. Ramsey
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Publication number: 20040135233Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.Type: ApplicationFiled: July 23, 2003Publication date: July 15, 2004Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
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Patent number: 6706621Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.Type: GrantFiled: November 22, 2002Date of Patent: March 16, 2004Assignee: International Business Machines CorporationInventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
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Publication number: 20030071329Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.Type: ApplicationFiled: November 22, 2002Publication date: April 17, 2003Applicant: International Business Machines CorporationInventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing