Patents by Inventor Leonard J. Gardecki

Leonard J. Gardecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7670437
    Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Duane E. Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard J. Gardecki, William L. Hammond, Kibby B. Horsford, Charles R. Ramsey
  • Publication number: 20080202421
    Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.
    Type: Application
    Filed: May 8, 2008
    Publication date: August 28, 2008
    Inventors: Duane E. Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard J. Gardecki, William L. Hammond, Kibby B. Horsford, Charles R. Ramsey
  • Patent number: 7410919
    Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: August 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Duane E Allen, Brian K Burnor, Thomas A Dotolo, Leonard J Gardecki, William L Hammond, Kibby B Horsford, Charles R Ramsey
  • Patent number: 7288492
    Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Leonard J. Gardecki, James R. Palmer, Erik M. Probstfield, Adolf E. Wirsing
  • Patent number: 7138326
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corp.
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Patent number: 6951775
    Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.
    Type: Grant
    Filed: June 28, 2003
    Date of Patent: October 4, 2005
    Assignee: International Business Machines Corporation
    Inventors: Leonard J. Gardecki, James R. Palmer, Erik M. Probstfield, Adolf E. Wirsing
  • Publication number: 20040266159
    Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.
    Type: Application
    Filed: June 28, 2003
    Publication date: December 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: Leonard J Gardecki, James R Palmer, Erik M Probstfield, Adolf E Wirsing
  • Publication number: 20040261977
    Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: Duane E. Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard J. Gardecki, William L. Hammond, Kibby B. Horsford, Charles R. Ramsey
  • Publication number: 20040135233
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Application
    Filed: July 23, 2003
    Publication date: July 15, 2004
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Patent number: 6706621
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Publication number: 20030071329
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Application
    Filed: November 22, 2002
    Publication date: April 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing