Patents by Inventor Leonard O. Turner

Leonard O. Turner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7010858
    Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventors: Leonard O. Turner, Tony Hamilton
  • Patent number: 6565369
    Abstract: An improved stacking connector. The connector includes a plug portion and a receptacle portion. The plug portion includes a plug signal pin and a plug impedance control pin located adjacent to the plug signal pin. The receptacle portion includes a receptacle signal pin for engaging the plug signal pin when the plug portion and the receptacle portion are in a mated position. The connector also includes an impedance control shield which is located adjacent to the plug signal pin or receptacle signal pin.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Hugo K. Schulz, Leonard O. Turner
  • Patent number: 6533613
    Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: March 18, 2003
    Assignee: Intel Corporation
    Inventors: Leonard O. Turner, Tony Hamilton
  • Patent number: 6503091
    Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: January 7, 2003
    Assignee: Intel Corporation
    Inventors: Frank P. Hart, Raviprakash Nagaraj, Leonard O. Turner, Arthur L. Spurrell
  • Publication number: 20020192994
    Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.
    Type: Application
    Filed: August 2, 2002
    Publication date: December 19, 2002
    Applicant: Intel Corporation, a California corporation
    Inventors: Leonard O. Turner, Tony Hamilton
  • Publication number: 20020016099
    Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.
    Type: Application
    Filed: October 2, 2001
    Publication date: February 7, 2002
    Inventors: Frank P. Hart, Raviprakash Nagaraj, Leonard O. Turner, Arthur L. Spurrell
  • Patent number: 6322370
    Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: November 27, 2001
    Assignee: Intel Corporation
    Inventors: Frank P. Hart, Raviprakash Nagaraj, Leonard O. Turner, Arthur L. Spurrell
  • Patent number: 6183266
    Abstract: An improved method and apparatus for transferring signals through a stacking connector. A disclosed apparatus includes a first engaging contact member mounted on a first circuit board and a second engaging contact member which removably engages the first engaging contact member mounted on a second circuit board. The first engaging contact member is electrically coupled to a first signal line on the first circuit board and the second engaging contact member is electrically coupled to a second signal line on the second circuit board. A conductive barrier partially surrounds the second engaging contact member. The barrier has at least one connector connecting the barrier to a bias voltage line.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: February 6, 2001
    Assignee: Intle Corporation
    Inventor: Leonard O. Turner
  • Patent number: 5603619
    Abstract: An apparatus for electrically connecting electrical contact pads on a first circuit board to electrical contact pads on a second circuit board is disclosed. Conductive bumps coupled to signal wires on a support element mate with the electrical contact pads on the first and second circuit boards. The mating provides an electrical connection allowing signals to be transmitted between the circuit boards. Alignment holes and alignment circuitry provide a means for verifying that the proper conductive bumps are mating with the proper electrical contact pads.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: February 18, 1997
    Assignee: Intel Corporation
    Inventors: Leonard O. Turner, Gerald A. Budelman, Mark B. Trobough
  • Patent number: 5111362
    Abstract: A rigid enclosure for printed circuit boards that utilizes identical top and bottom covers and provides for offsetting the distance the printed circuit board sits from the bottom cover. The enclosure utilizes features formed into the covers to provide for alignment and fastening. Removable vents provide for air flow to cool the printed circuit board and when removed, allow access for interface to the printed circuit board. Threaded inserts and standoffs provide flexibility for fastening identical parts together.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: May 5, 1992
    Assignee: Intel Corporation
    Inventors: Ronald C. Flamm, Leonard O. Turner, James D. Plunkett
  • Patent number: 5057023
    Abstract: A connection system for use in connecting a high density flexible circuit directly to a surface mounted integrated circuit component mounted on a printed circuit board. The connection system utilizes an upper and lower stiffener plate to route the contacts of the high density flexible circuit to the pins of the integrated circuit component. The connection system utilizes silicone rubber pressure rods to create a force on the contacts of the higher density flexible circuit to ensure reliable connection to the leads of the surface mounted components. The connection system utilizes comb spacers which define slots to align the contacts of the high density circuit to the pins of the integrated circuit component and a top clamp to retain the assembly onto the integrated circuit component.
    Type: Grant
    Filed: June 1, 1990
    Date of Patent: October 15, 1991
    Assignee: Intel Corporation
    Inventors: Ashok N. Kabadi, Leonard O. Turner, Ronald C. Flamm
  • Patent number: 4798918
    Abstract: A high density flexible circuit for coupling electrical devices. The flexible circuit has signal and ground traces on both sides of the flexible circuit. Each signal trace is surrounded by ground traces. There is a ground trace on either side of each signal trace and two ground traces located below each signal trace. This system of placing ground traces surrounding each signal trace reduces electrical noise between the signal traces and reduces the electrical capacitance of the circuit.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: January 17, 1989
    Assignee: Intel Corporation
    Inventors: Ashok N. Kabadi, Leonard O. Turner, Michael T. White